Datasheet > IDT71V547XS

IDT71V547XS

更新时间： 2024-11-20 01:19:47

品牌	Logo	应用领域
艾迪悌 - IDT		静态存储器
页数	文件大小	规格书
20页	711K
描述
Synchronous SRAM

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中文翻译

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数据手册

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IDT71V547XS 数据手册

128K X 36, 3.3V Synchronous IDT71V547S/XS

SRAM with ZBT™ Feature, Burst

Counter and Flow-Through Outputs

Features

◆

Single R/W (READ/WRITE) control pin

◆

128K x 36 memory configuration, flow-through outputs

Supports high performance system speed - 95 MHz

(8ns Clock-to-Data Access)

◆

4-word burst capability (Interleaved or linear)

Individual byte write (BW1 - BW4) control (May tie active)

Three chip enables for simple depth expansion

Single 3.3V power supply (±5%)

◆

ZBT^TMFeature - No dead cycles between write and read

cycles

Packaged in a JEDEC standard 100-pin TQFP package

Internally synchronized signal eliminates the need to

control OE

FunctionalBlockDiagram

128K x 36 BIT

MEMORY ARRAY

LBO

Address A [0:16]

Address

CE1, CE2, CE2

R/W

Control

CEN

ADV/LD

BWx

Control Logic

Clk

Mux

Sel

Clock

Gate

Data I/O [0:31], I/O P[1:4]

3822 drw 01

ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola Inc.

FEBRUARY 2015

DSC-3822/07

12 3 4 5 6 7...20

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