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IDT71V547XS100PFI PDF预览

IDT71V547XS100PFI

更新时间： 2024-11-23 21:18:07
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器内存集成电路
页数 文件大小 规格书
19页 1363K
描述
ZBT SRAM, 128KX36, CMOS, PQFP100, 14 X 20 MM, PLASTIC, TQFP-100

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IDT71V547XS100PFI 技术参数

是否无铅：含铅是否Rohs认证：不符合
生命周期：Obsolete零件包装代码：QFP
包装说明：LQFP,针数：100
Reach Compliance Code：compliantECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.82
Is Samacsys：N其他特性：FLOW-THROUGH ARCHITECTURE
JESD-30 代码：R-PQFP-G100JESD-609代码：e0
长度：20 mm内存密度：4718592 bit
内存集成电路类型：ZBT SRAM内存宽度：36
湿度敏感等级：3功能数量：1
端子数量：100字数：131072 words
字数代码：128000工作模式：SYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：128KX36封装主体材料：PLASTIC/EPOXY
封装代码：LQFP封装形状：RECTANGULAR
封装形式：FLATPACK, LOW PROFILE并行/串行：PARALLEL
峰值回流温度（摄氏度）：240认证状态：Not Qualified
座面最大高度：1.6 mm最大供电电压 (Vsup)：3.465 V
最小供电电压 (Vsup)：3.135 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：GULL WING端子节距：0.65 mm
端子位置：QUAD处于峰值回流温度下的最长时间：20
宽度：14 mmBase Number Matches：1

IDT71V547XS100PFI 数据手册

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128K X 36, 3.3V Synchronous IDT71V547S/XS  
SRAM with ZBT™ Feature, Burst  
Counter and Flow-Through Outputs  
Features  
◆
128K x 36 memory configuration, flow-through outputs  
Supports high performance system speed - 95 MHz  
(8ns Clock-to-Data Access)  
TheIDT71V547containsaddress,data-inandcontrolsignalregisters.  
Theoutputsareflow-through(nooutputdataregister).Outputenableis  
theonlyasynchronoussignalandcanbeusedtodisabletheoutputsat  
anygiventime.  
A Clock Enable (CEN) pin allows operation of the IDT71V547 to  
be suspended as long as necessary. All synchronous inputs are  
ignored when CEN is high and the internal device registers will hold  
their previous values.  
Therearethreechipenablepins(CE1,CE2,CE2)thatallowtheuser  
todeselectthedevicewhendesired. Ifanyoneofthesethreeisnotactive  
whenADV/LDislow,nonewmemoryoperationcanbeinitiatedandany  
burstinprogressisstopped.However,anypendingdatatransfers(reads  
orwrites)willbecompleted.Thedatabuswilltri-stateonecycleafterthe  
chipwasdeselectedorwriteinitiated.  
◆
◆
◆
ZBTTM Feature - No dead cycles between write and read  
cycles  
Internally synchronized signal eliminates the need to  
control OE  
◆
◆
◆
◆
◆
◆
Single R/W (READ/WRITE) control pin  
4-word burst capability (Interleaved or linear)  
Individual byte write (BW1 - BW4) control (May tie active)  
Three chip enables for simple depth expansion  
Single 3.3V power supply (±5%)  
Packaged in a JEDEC standard 100-pin TQFP package  
TheIDT71V547hasanon-chipburstcounter. Intheburstmode,the  
IDT71V547canprovidefourcyclesofdataforasingleaddresspresented  
totheSRAM.TheorderoftheburstsequenceisdefinedbytheLBOinput  
pin. TheLBOpinselectsbetweenlinearandinterleavedburstsequence.  
The ADV/LD signal is used to load a new external address (ADV/LD =  
LOW)orincrementtheinternalburstcounter(ADV/LD=HIGH).  
TheIDT71V547SRAMutilizesIDT'shigh-performance,high-volume  
3.3V CMOS process, and is packaged in a JEDEC Standard 14mm x  
20mm100-pinthinplasticquadflatpack(TQFP)forhighboarddensity.  
Description  
The IDT71V547 is a 3.3V high-speed 4,718,592-bit (4.5 Megabit)  
synchronousSRAMorganizedas128Kx36bits. Itisdesignedtoeliminate  
deadbuscycleswhenturningthebusaroundbetweenreadsandwrites,  
orwritesandreads.ThusithasbeengiventhenameZBTTM,orZeroBus  
Turn-around.  
AddressandcontrolsignalsareappliedtotheSRAMduringoneclock  
cycle,andonthenextclockcycle,itsassociateddatacycleoccurs,beit  
read or write.  
PinDescriptionSummary  
A
0
- A16  
Address Inputs  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
I/O  
Synchronous  
Synchronous  
Asynchronous  
Synchronous  
Synchronous  
Synchronous  
N/A  
Three Chip Enables  
Output Enable  
CE  
1
, CE  
2, CE  
2
OE  
R/W  
Read/Write Signal  
Clock Enable  
CEN  
Individual Byte Write Selects  
Clock  
BW  
1
, BW  
2
, BW  
3
, BW  
4
CLK  
ADV/LD  
Advance Burst Address / Load New Address  
Linear / Interleaved Burst Order  
Data Input/Output  
3.3V Power  
Synchronous  
Static  
LBO  
- I/O31, I/OP1  
I/OP4  
I/O  
0
-
Synchronous  
Static  
V
DD  
Supply  
Supply  
VSS  
Ground  
Static  
3822 tbl 01  
ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola Inc.  
OCTOBER 2008  
1
DSC-3822/04  
©2007IntegratedDeviceTechnology,Inc.  
1234567...19

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