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IDT71V547S90PFI8 PDF预览

IDT71V547S90PFI8

更新时间: 2024-11-19 15:34:47
品牌 Logo 应用领域
艾迪悌 - IDT 时钟静态存储器内存集成电路
页数 文件大小 规格书
20页 704K
描述
ZBT SRAM, 128KX36, 9ns, CMOS, PQFP100, 14 X 20 MM, PLASTIC, TQFP-100

IDT71V547S90PFI8 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:QFP包装说明:14 X 20 MM, PLASTIC, TQFP-100
针数:100Reach Compliance Code:not_compliant
ECCN代码:3A991.B.2.AHTS代码:8542.32.00.41
风险等级:5.63最长访问时间:9 ns
其他特性:FLOW-THROUGH ARCHITECTURE最大时钟频率 (fCLK):83 MHz
I/O 类型:COMMONJESD-30 代码:R-PQFP-G100
JESD-609代码:e0长度:20 mm
内存密度:4718592 bit内存集成电路类型:ZBT SRAM
内存宽度:36湿度敏感等级:3
功能数量:1端子数量:100
字数:131072 words字数代码:128000
工作模式:SYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:128KX36
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:LQFP封装等效代码:QFP100,.63X.87
封装形状:RECTANGULAR封装形式:FLATPACK, LOW PROFILE
并行/串行:PARALLEL峰值回流温度(摄氏度):240
电源:3.3 V认证状态:Not Qualified
座面最大高度:1.6 mm最大待机电流:0.045 A
最小待机电流:3.14 V子类别:SRAMs
最大压摆率:0.235 mA最大供电电压 (Vsup):3.465 V
最小供电电压 (Vsup):3.135 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn85Pb15)
端子形式:GULL WING端子节距:0.65 mm
端子位置:QUAD处于峰值回流温度下的最长时间:20
宽度:14 mmBase Number Matches:1

IDT71V547S90PFI8 数据手册

 浏览型号IDT71V547S90PFI8的Datasheet PDF文件第2页浏览型号IDT71V547S90PFI8的Datasheet PDF文件第3页浏览型号IDT71V547S90PFI8的Datasheet PDF文件第4页浏览型号IDT71V547S90PFI8的Datasheet PDF文件第5页浏览型号IDT71V547S90PFI8的Datasheet PDF文件第6页浏览型号IDT71V547S90PFI8的Datasheet PDF文件第7页 
128K X 36, 3.3V Synchronous IDT71V547S/XS  
SRAM with ZBT™ Feature, Burst  
Counter and Flow-Through Outputs  
Features  
Single R/W (READ/WRITE) control pin  
128K x 36 memory configuration, flow-through outputs  
Supports high performance system speed - 95 MHz  
(8ns Clock-to-Data Access)  
4-word burst capability (Interleaved or linear)  
Individual byte write (BW1 - BW4) control (May tie active)  
Three chip enables for simple depth expansion  
Single 3.3V power supply (±5%)  
ZBTTM Feature - No dead cycles between write and read  
cycles  
Packaged in a JEDEC standard 100-pin TQFP package  
Internally synchronized signal eliminates the need to  
control OE  
FunctionalBlockDiagram  
128K x 36 BIT  
MEMORY ARRAY  
LBO  
Address A [0:16]  
D
D
Q
Q
Address  
CE1, CE2, CE2  
R/W  
Control  
CEN  
ADV/LD  
DI  
DO  
BWx  
D
Q
Control Logic  
Clk  
Mux  
Sel  
Clock  
Gate  
OE  
,
Data I/O [0:31], I/O P[1:4]  
3822 drw 01  
ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola Inc.  
FEBRUARY 2015  
1
DSC-3822/07  
©2015 Integrated Device Technology, Inc.  

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