Datasheet > IDT71V3568S100BG

IDT71V3568S100BG

更新时间： 2024-09-14 14:33:59

品牌	Logo	应用领域
艾迪悌 - IDT		静态存储器内存集成电路
页数	文件大小	规格书
23页	305K
描述
ZBT SRAM, 256KX18, 5.33ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, BGA-119

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IDT71V3568S100BG 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Active	零件包装代码：	BGA
包装说明：	14 X 22 MM, PLASTIC, BGA-119	针数：	119
Reach Compliance Code：	compliant	ECCN代码：	3A991.B.2.A
HTS代码：	8542.32.00.41	风险等级：	5.87
最长访问时间：	5.33 ns	JESD-30 代码：	R-PBGA-B119
JESD-609代码：	e0	长度：	22 mm
内存密度：	4718592 bit	内存集成电路类型：	ZBT SRAM
内存宽度：	18	湿度敏感等级：	3
功能数量：	1	端子数量：	119
字数：	262144 words	字数代码：	256000
工作模式：	SYNCHRONOUS	最高工作温度：	70 °C
最低工作温度：		组织：	256KX18
封装主体材料：	PLASTIC/EPOXY	封装代码：	BGA
封装形状：	RECTANGULAR	封装形式：	GRID ARRAY
并行/串行：	PARALLEL	峰值回流温度（摄氏度）：	225
认证状态：	Not Qualified	座面最大高度：	3.5 mm
最大供电电压 (Vsup)：	3.465 V	最小供电电压 (Vsup)：	3.135 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	TIN LEAD	端子形式：	BALL
端子节距：	1.27 mm	端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	20	宽度：	14 mm
Base Number Matches：	1

IDT71V3568S100BG 数据手册

128K x 36, 256K x 18

Preliminary

IDT71V3566

IDT71V3568

SmartZBT™3.3VSynchronousSRAMs

3.3V I/O, Burst Counter

PipelinedOutputs

Features

Description

◆

128K x 36, 256K x 18 memory configurations

TheIDT71V3566/68are3.3Vhigh-speed4,718,592-bit(4.5Mega-

bit) synchronous SRAMs. They are designed to eliminate dead bus

cycles when turning the bus around between reads and writes, or

writes and reads. Thus, they have been given the name ZBT^TM, or

Zero Bus Turnaround.

◆

Supports high performance system speed - from 66MHz to

133MHz

◆

ZBT^TMFeature - No dead cycles between write and read

cycles

◆

Smart ZBT^TMFeature - Eases system timing requirements

Address and control signals are applied to the SRAM during one

clockcycle,andtwocycleslatertheassociateddatacycleoccurs,beit

read or write.

and reduces the likelihood of bus contention

With Smart ZBT^TMthe output turn-on (tCLZ) is adaptable to

◆

the user's system and is a function of the cycle time

Backward compatible with IDT's existing ZBT offerings

Internally synchronized output buffer enable eliminates the and reads. Traditionally, SRAMs are designed with fast turn-on times

TheIDT71V3566/68offertheuseraSmartfunctionalitywhichsimplifies

systemtimingrequirementswhenturningthebusaroundbetweenwrites

◆

need to control OE

(tCLZ)inordertomeettherequirementsofhighspeedapplications.This

fastturn-onmayleadtobuscontentionatslowerspeeds,i.e.133MHzand

slower,sincethesedesignsoftenuselessaggressiveASICs/controllers

withlooseturn-offparameters(tCHZ).Thusatslowerspeeds,moremargin

ontheRAM'stCLZmaybeneededtocompensatefortheslowturn-offof

theASIC/controller.TheIDT71V3566/68havetheabilitytoprovidethis

extra marginbyallowingtCLZ toadapttothe user's system.

WiththeSmartZBT^TMfeature,theoutputturn-ontime(tCLZ)adaptsto

theuser'ssystemandissolelyafunctionofcycletime(tCYC).Thuswith

SmartZBT^TM,tCLZisindependentofprocess,voltage,andtemperature

variations.Withthisdeterministicoutputturn-onfeature,theguessworkof

when the SRAM begins to drive the bus is removed, therefore easing

◆

Single R/W (READ/WRITE) control pin

Positive clock-edge triggered address, data, and control

signal registers for fully pipelined applications

4-word burst capability (interleaved or linear)

Individual byte write (BW1 - BW4) control (May tie active)

Three chip enables for simple depth expansion

3.3V power supply (±5%)

3.3V I/O Supply (VDDQ)

Packaged in a JEDEC standard 100-lead plastic thin quad

flatpack (TQFP) and 119-lead ball grid array (BGA).

◆

PinDescriptionSummary

-A17

Addres s Inputs

Input

I/O

Synchronous

As ynchronous

Synchronous

N/A

Chip Enables

, CE

Output Enable

Re ad/Write Signal

Clock Enable

CEN

Individual Byte Write Se le cts

Clock

CLK

ADV/LD

Advance burst addre ss / Load new addre ss

Line ar / Inte rle aved Burs t Orde r

Data Input / Outp ut

Core Powe r, I/O Power

Ground

Synchronous

Static

LBO

I/O

-I/O31, I/OP 1-I/OP 4

DD, VDDQ

S S

Synchronous

Static

Supply

Static

5295 tbl 01

ZBT and ZeroBus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola Inc.

Smart ZBT and Smart Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is also supported by Micron Technology, Inc.

DECEMBER 1999

DSC-5295/00

12 3 4 5 6 7...23

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与IDT71V3568S100BG相关器件

型号	品牌	获取价格	描述	数据表
IDT71V3568S133BG	IDT	获取价格	ZBT SRAM, 256KX18, 4.5ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, BGA-119
IDT71V35761	IDT	获取价格	128K x 36, 256K x 18 3.3V Synchronous SRAMs 3.3V I/O, Pipelined Outputs Burst Counter, Sin
IDT71V35761183PFI	IDT	获取价格	Cache SRAM, 128KX36, 3.3ns, CMOS, PQFP100, PLASTIC, TQFP-100
IDT71V3576133BG	IDT	获取价格	Cache SRAM, 128KX36, 4.2ns, CMOS, PBGA119, BGA-119
IDT71V3576133PF	IDT	获取价格	Cache SRAM, 128KX36, 4.2ns, CMOS, PQFP100, 14 X 20 MM, PLASTIC, TQFP-100
IDT71V3576150BG	IDT	获取价格	Cache SRAM, 128KX36, 3.8ns, CMOS, PBGA119, BGA-119
IDT71V3576150PF	IDT	获取价格	Cache SRAM, 128KX36, 3.8ns, CMOS, PQFP100, 14 X 20 MM, PLASTIC, TQFP-100
IDT71V3576183BG	IDT	获取价格	Standard SRAM, 128KX36, 3.3ns, CMOS, PBGA119, BGA-119
IDT71V35761S	IDT	获取价格	128K x 36, 256K x 18 3.3V Synchronous SRAMs 3.3V I/O, Pipelined Outputs Burst Counter, Sin
IDT71V35761S_14	IDT	获取价格	3.3V Synchronous SRAMs 3.3V I/O, Pipelined Outputs Burst Counter, Single Cycle Deselect

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