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IDT71V35761S166BQ8 PDF预览

IDT71V35761S166BQ8

更新时间: 2024-11-15 20:05:15
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器内存集成电路
页数 文件大小 规格书
21页 824K
描述
Cache SRAM, 128KX36, 3.5ns, CMOS, PBGA165, FBGA-165

IDT71V35761S166BQ8 技术参数

生命周期:Obsolete零件包装代码:BGA
包装说明:TBGA,针数:165
Reach Compliance Code:unknownECCN代码:3A991.B.2.A
HTS代码:8542.32.00.41风险等级:5.61
最长访问时间:3.5 ns其他特性:PIPELINED ARCHITECTURE
JESD-30 代码:R-PBGA-B165JESD-609代码:e0
长度:15 mm内存密度:4718592 bit
内存集成电路类型:CACHE SRAM内存宽度:36
功能数量:1端子数量:165
字数:131072 words字数代码:128000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:128KX36
封装主体材料:PLASTIC/EPOXY封装代码:TBGA
封装形状:RECTANGULAR封装形式:GRID ARRAY, THIN PROFILE
并行/串行:PARALLEL认证状态:Not Qualified
座面最大高度:1.2 mm最大供电电压 (Vsup):3.465 V
最小供电电压 (Vsup):3.135 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:TIN LEAD
端子形式:BALL端子节距:1 mm
端子位置:BOTTOM宽度:13 mm
Base Number Matches:1

IDT71V35761S166BQ8 数据手册

 浏览型号IDT71V35761S166BQ8的Datasheet PDF文件第2页浏览型号IDT71V35761S166BQ8的Datasheet PDF文件第3页浏览型号IDT71V35761S166BQ8的Datasheet PDF文件第4页浏览型号IDT71V35761S166BQ8的Datasheet PDF文件第5页浏览型号IDT71V35761S166BQ8的Datasheet PDF文件第6页浏览型号IDT71V35761S166BQ8的Datasheet PDF文件第7页 
128K x 36  
IDT71V35761S/SA  
3.3VSynchronousSRAMs  
3.3VI/O,PipelinedOutputs  
BurstCounter,SingleCycleDeselect  
Self-timed write cycle with global write control (GW), byte  
write enable (BWE), and byte writes (BWx)  
Power down controlled by ZZ input  
Features  
128K x 36 memory configurations  
Supports high system speed:  
3.3V I/O  
Commercial:  
Optional - Boundary Scan JTAG Interface (IEEE 1149.1  
compliant)  
– 200MHz 3.1ns clock access time  
CommercialandIndustrial:  
Packaged in a JEDEC Standard 100-pin plastic thin quad  
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine  
pitch ball grid array  
– 183MHz 3.3ns clock access time  
– 166MHz 3.5ns clock access time  
LBO input selects interleaved or linear burst mode  
Green parts available, see ordering information  
3.3V core power supply  
FunctionalBlockDiagram  
LBO  
ADV  
INTERNAL  
ADDRESS  
CEN  
128K x 36-  
CLK  
2
Burst  
Logic  
17/18  
Binary  
BIT  
Counter  
ADSC  
A0*  
A1*  
MEMORY  
ARRAY  
Q0  
Q1  
CLR  
ADSP  
2
CLK EN  
A0,A1  
A2–A17  
A0 -  
A
16/17  
ADDRESS  
REGISTER  
36  
36  
17/18  
GW  
Byte 1  
Write Register  
BWE  
Byte 1  
Write Driver  
BW  
BW  
1
2
9
9
Byte 2  
Write Register  
Byte 2  
Write Driver  
Byte 3  
Write Register  
Byte 3  
Write Driver  
BW  
BW  
3
4
9
9
Byte 4  
Write Register  
Byte 4  
Write Driver  
OUTPUT  
REGISTER  
CE  
CS  
CS  
Q
D
0
Enable  
Register  
CLK EN  
DATA  
1
INPUT  
REGISTER  
ZZ  
Powerdown  
D
Q
Enable  
Delay  
Register  
OE  
OUTPUT  
BUFFER  
OE  
,
36  
I/O  
0 — I/O31  
I/OP1 — I/OP4  
5301 drw 01  
TMS  
TDI  
TCK  
JTAG  
(SA Version)  
TDO  
TRST  
(Optional)  
NOVEMBER2014  
1
©2014 Integrated Device Technology, Inc.  
DSC-5301/07  

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