Datasheet > 存储 > SRAM> IDT71V35761S183PF

IDT71V35761S183PF

更新时间： 2024-11-04 22:23:55

品牌	Logo	应用领域
艾迪悌 - IDT		计数器静态存储器
页数	文件大小	规格书
22页	283K
描述
128K x 36, 256K x 18 3.3V Synchronous SRAMs 3.3V I/O, Pipelined Outputs Burst Counter, Single Cycle Deselect

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128K x 36, 256K x 18

IDT71V35761S

IDT71V35781S

IDT71V35761SA

IDT71V35781SA

3.3VSynchronousSRAMs

3.3VI/O,PipelinedOutputs

BurstCounter,SingleCycleDeselect

Features

Description

◆

128K x 36, 256K x 18 memory configurations

The IDT71V35761/781 are high-speed SRAMs organized as

128Kx36/256Kx18.TheIDT71V35761/781SRAMscontainwrite,data,

addressandcontrolregisters. InternallogicallowstheSRAMtogenerate

aself-timedwritebaseduponadecisionwhichcanbeleftuntiltheendof

thewritecycle.

◆

Supports high system speed:

Commercial:

– 200MHz 3.1ns clock access time

CommercialandIndustrial:

– 183MHz 3.3ns clock access time

– 166MHz 3.5ns clock access time

LBO input selects interleaved or linear burst mode

Theburstmodefeatureoffersthehighestlevelofperformancetothe

systemdesigner,astheIDT71V35761/81canprovidefourcyclesofdata

forasingleaddress presentedtotheSRAM. Aninternalburstaddress

◆

Self-timedwritecyclewithglobalwritecontrol(GW),bytewrite counteracceptsthefirstcycleaddressfromtheprocessor,initiatingthe

enable (BWE), and byte writes (BWx)

3.3V core power supply

Power down controlled by ZZ input

3.3V I/O

accesssequence.Thefirstcycleofoutputdatawillbepipelinedforone

cycle before it is available on the next rising clock edge. If burst mode

operationisselected(ADV=LOW),thesubsequentthreecyclesofoutput

datawillbeavailabletotheuseronthenextthreerisingclockedges. The

◆

Optional - Boundary Scan JTAG Interface (IEEE 1149.1 orderofthesethreeaddressesaredefinedbytheinternalburstcounter

compliant)

andthe LBO inputpin.

◆

Packaged in a JEDEC Standard 100-pin plastic thin quad

TheIDT71V35761/781SRAMsutilizeIDT’slatesthigh-performance

flatpack(TQFP),119ballgridarray(BGA)and165finepitchball CMOSprocessandarepackagedinaJEDECstandard14mmx20mm

grid array

100-pin thinplasticquadflatpack(TQFP)aswellasa119ballgridarray

(BGA) and 165 fine pitch ball grid array.

PinDescriptionSummary

A0-A17

Address Inputs

Input

Output

Input

I/O

Synchronous

Asynchronous

Synchronous

N/A

Chip Enable

CS0, CS¹

Chip Selects

Output Enable

Global Write Enable

Byte Write Enable

Individual Byte Write Selects

Clock

BWE

(1)

BW¹, BW², BW³, BW⁴

CLK

Burst Address Advance

Address Status (Cache Controller)

Address Status (Processor)

Linear / Interleaved Burst Order

Test Mode Select

Test Data Input

Synchronous

ADV

ADSC

ADSP

LBO

TMS

Synchronous

N/A

TDI

TCK

Test Clock

TDO

Test Data Output

Synchronous

Asynchronous

Synchronous

N/A

JTAG Reset (Optional)

Sleep Mode

TRST

I/O0-I/O31, I/OP1-I/OP4

VDD, VDDQ

Data Input / Output

Core Power, I/O Power

Ground

Supply

V^SS

N/A

NOTE:

5301 tbl 01

1. BW3 and BW4 are not applicable for the IDT71V35781.

JUNE 2003

DSC-5301/03

12 3 4 5 6 7...22

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与IDT71V35761S183PF相关器件

型号	品牌	获取价格	描述	数据表
IDT71V35761S183PF8	IDT	获取价格	Cache SRAM, 128KX36, 3.3ns, CMOS, PQFP100, 14 X 20 MM, PLASTIC, TQFP-100
IDT71V35761S183PFG	IDT	获取价格	3.3V Synchronous SRAMs 3.3V I/O, Pipelined Outputs Burst Counter, Single Cycle Deselect
IDT71V35761S183PFG8	IDT	获取价格	3.3V Synchronous SRAMs 3.3V I/O, Pipelined Outputs Burst Counter, Single Cycle Deselect
IDT71V35761S183PFGI	IDT	获取价格	Cache SRAM, 128KX36, 3.3ns, CMOS, PQFP100, 14 X 20 MM, PLASTIC, TQFP-100
IDT71V35761S183PFGI8	IDT	获取价格	3.3V Synchronous SRAMs 3.3V I/O, Pipelined Outputs Burst Counter, Single Cycle Deselect
IDT71V35761S183PFI	IDT	获取价格	128K x 36, 256K x 18 3.3V Synchronous SRAMs 3.3V I/O, Pipelined Outputs Burst Counter, Sin
IDT71V35761S183PFI8	IDT	获取价格	Cache SRAM, 128KX36, 3.3ns, CMOS, PQFP100, 14 X 20 MM, PLASTIC, TQFP-100
IDT71V35761S183PFI9	IDT	获取价格	Cache SRAM, 128KX36, 3.3ns, CMOS, PQFP100, 14 X 20 MM, PLASTIC, TQFP-100
IDT71V35761S200BG	IDT	获取价格	128K x 36, 256K x 18 3.3V Synchronous SRAMs 3.3V I/O, Pipelined Outputs Burst Counter, Sin
IDT71V35761S200BGG	IDT	获取价格	3.3V Synchronous SRAMs 3.3V I/O, Pipelined Outputs Burst Counter, Single Cycle Deselect

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