Datasheet > IDT71V35761183PFI

IDT71V35761183PFI

更新时间： 2024-09-15 10:16:27

品牌	Logo	应用领域
艾迪悌 - IDT		静态存储器
页数	文件大小	规格书
23页	519K
描述
Cache SRAM, 128KX36, 3.3ns, CMOS, PQFP100, PLASTIC, TQFP-100

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中文翻译

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128K x 36, 256K x 18

IDT71V35761

IDT71V35781

3.3VSynchronousSRAMs

3.3VI/O,PipelinedOutputs

BurstCounter,SingleCycleDeselect

Features

Description

◆

128K x 36, 256K x 18 memory configurations

The IDT71V35761/781 are high-speed SRAMs organized as

128Kx36/256Kx18.TheIDT71V35761/781SRAMscontainwrite,data,

addressandcontrolregisters. InternallogicallowstheSRAMtogenerate

aself-timedwritebaseduponadecisionwhichcanbeleftuntiltheendof

thewritecycle.

◆

Supports high system speed:

Commercial:

– 200MHz 3.1ns clock access time

CommercialandIndustrial:

– 183MHz 3.3ns clock access time

– 166MHz 3.5ns clock access time

LBO input selects interleaved or linear burst mode

Theburstmodefeatureoffersthehighestlevelofperformancetothe

systemdesigner,astheIDT71V35761/81canprovidefourcyclesofdata

forasingleaddress presentedtotheSRAM. Aninternalburstaddress

◆

Self-timedwritecyclewithglobalwritecontrol(GW),bytewrite counteracceptsthefirstcycleaddressfromtheprocessor,initiatingthe

enable (BWE), and byte writes (BWx)

3.3V core power supply

Power down controlled by ZZ input

3.3V I/O

Packaged in a JEDEC Standard 100-pin plastic thin quad orderofthesethreeaddressesaredefinedbytheinternalburstcounter

flatpack(TQFP),119ballgridarray(BGA)and165finepitchball andthe LBO inputpin.

grid array

accesssequence.Thefirstcycleofoutputdatawillbepipelinedforone

cycle before it is available on the next rising clock edge. If burst mode

operationisselected(ADV=LOW),thesubsequentthreecyclesofoutput

datawillbeavailabletotheuseronthenextthreerisingclockedges. The

◆

TheIDT71V35761/781SRAMsutilizeIDT’slatesthigh-performance

CMOSprocessandarepackagedinaJEDECstandard14mmx20mm

100-pin thinplasticquadflatpack(TQFP)aswellasa119ballgridarray

(BGA) and 165 fine pitch ball grid array.

PinDescriptionSummary

A -A

Address Inputs

Input

I/O

Synchronous

Asynchronous

Synchronous

N/A

Chip Enable

CS , CS

Chip Selects

Output Enable

Global Write Enable

Byte Write Enable

Individual Byte Write Selects

Clock

BWE

(1)

¹,

²,

³,

BW BW BW BW

CLK

ADV

ADSC

ADSP

LBO

Burst Address Advance

Address Status (Cache Controller)

Address Status (Processor)

Linear / Interleaved Burst Order

Sleep Mode

Synchronous

Asynchronous

Synchronous

N/A

I/O -I/O , I/O -I/O

Data Input / Output

Core Power, I/O Power

Ground

DD DDQ

V , V

Supply

N/A

5301 tbl 01

NOTE:

1. BW3 and BW4 are not applicable for the IDT71V35781.

OCTOBER 2000

DSC-5301/01

12 3 4 5 6 7...23

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与IDT71V35761183PFI相关器件

型号	品牌	获取价格	描述	数据表
IDT71V3576133BG	IDT	获取价格	Cache SRAM, 128KX36, 4.2ns, CMOS, PBGA119, BGA-119
IDT71V3576133PF	IDT	获取价格	Cache SRAM, 128KX36, 4.2ns, CMOS, PQFP100, 14 X 20 MM, PLASTIC, TQFP-100
IDT71V3576150BG	IDT	获取价格	Cache SRAM, 128KX36, 3.8ns, CMOS, PBGA119, BGA-119
IDT71V3576150PF	IDT	获取价格	Cache SRAM, 128KX36, 3.8ns, CMOS, PQFP100, 14 X 20 MM, PLASTIC, TQFP-100
IDT71V3576183BG	IDT	获取价格	Standard SRAM, 128KX36, 3.3ns, CMOS, PBGA119, BGA-119
IDT71V35761S	IDT	获取价格	128K x 36, 256K x 18 3.3V Synchronous SRAMs 3.3V I/O, Pipelined Outputs Burst Counter, Sin
IDT71V35761S_14	IDT	获取价格	3.3V Synchronous SRAMs 3.3V I/O, Pipelined Outputs Burst Counter, Single Cycle Deselect
IDT71V35761S166B	IDT	获取价格	Cache SRAM, 128KX36, 3.5ns, CMOS, PBGA119, BGA-119
IDT71V35761S166BG	IDT	获取价格	128K x 36, 256K x 18 3.3V Synchronous SRAMs 3.3V I/O, Pipelined Outputs Burst Counter, Sin
IDT71V35761S166BG8	IDT	获取价格	Cache SRAM, 128KX36, 3.5ns, CMOS, PBGA119, BGA-119

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