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IDT71V35761183PFI PDF预览

IDT71V35761183PFI

更新时间: 2024-11-16 10:16:27
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器
页数 文件大小 规格书
23页 519K
描述
Cache SRAM, 128KX36, 3.3ns, CMOS, PQFP100, PLASTIC, TQFP-100

IDT71V35761183PFI 数据手册

 浏览型号IDT71V35761183PFI的Datasheet PDF文件第2页浏览型号IDT71V35761183PFI的Datasheet PDF文件第3页浏览型号IDT71V35761183PFI的Datasheet PDF文件第4页浏览型号IDT71V35761183PFI的Datasheet PDF文件第5页浏览型号IDT71V35761183PFI的Datasheet PDF文件第6页浏览型号IDT71V35761183PFI的Datasheet PDF文件第7页 
128K x 36, 256K x 18  
IDT71V35761  
IDT71V35781  
3.3VSynchronousSRAMs  
3.3VI/O,PipelinedOutputs  
BurstCounter,SingleCycleDeselect  
Features  
Description  
128K x 36, 256K x 18 memory configurations  
The IDT71V35761/781 are high-speed SRAMs organized as  
128Kx36/256Kx18.TheIDT71V35761/781SRAMscontainwrite,data,  
addressandcontrolregisters. InternallogicallowstheSRAMtogenerate  
aself-timedwritebaseduponadecisionwhichcanbeleftuntiltheendof  
thewritecycle.  
Supports high system speed:  
Commercial:  
– 200MHz 3.1ns clock access time  
CommercialandIndustrial:  
– 183MHz 3.3ns clock access time  
– 166MHz 3.5ns clock access time  
LBO input selects interleaved or linear burst mode  
Theburstmodefeatureoffersthehighestlevelofperformancetothe  
systemdesigner,astheIDT71V35761/81canprovidefourcyclesofdata  
forasingleaddress presentedtotheSRAM. Aninternalburstaddress  
Self-timedwritecyclewithglobalwritecontrol(GW),bytewrite counteracceptsthefirstcycleaddressfromtheprocessor,initiatingthe  
enable (BWE), and byte writes (BWx)  
3.3V core power supply  
Power down controlled by ZZ input  
3.3V I/O  
Packaged in a JEDEC Standard 100-pin plastic thin quad orderofthesethreeaddressesaredefinedbytheinternalburstcounter  
flatpack(TQFP),119ballgridarray(BGA)and165finepitchball andthe LBO inputpin.  
grid array  
accesssequence.Thefirstcycleofoutputdatawillbepipelinedforone  
cycle before it is available on the next rising clock edge. If burst mode  
operationisselected(ADV=LOW),thesubsequentthreecyclesofoutput  
datawillbeavailabletotheuseronthenextthreerisingclockedges. The  
TheIDT71V35761/781SRAMsutilizeIDT’slatesthigh-performance  
CMOSprocessandarepackagedinaJEDECstandard14mmx20mm  
100-pin thinplasticquadflatpack(TQFP)aswellasa119ballgridarray  
(BGA) and 165 fine pitch ball grid array.  
PinDescriptionSummary  
0
17  
A -A  
Address Inputs  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
I/O  
Synchronous  
Synchronous  
Synchronous  
Asynchronous  
Synchronous  
Synchronous  
Synchronous  
N/A  
Chip Enable  
CE  
0
1
CS , CS  
Chip Selects  
Output Enable  
OE  
Global Write Enable  
Byte Write Enable  
Individual Byte Write Selects  
Clock  
GW  
BWE  
(1)  
1,  
2,  
3,  
4
BW BW BW BW  
CLK  
ADV  
ADSC  
ADSP  
LBO  
Burst Address Advance  
Address Status (Cache Controller)  
Address Status (Processor)  
Linear / Interleaved Burst Order  
Sleep Mode  
Synchronous  
Synchronous  
Synchronous  
DC  
ZZ  
Asynchronous  
Synchronous  
N/A  
0
31  
P1  
P4  
I/O -I/O , I/O -I/O  
Data Input / Output  
Core Power, I/O Power  
Ground  
DD DDQ  
V , V  
Supply  
Supply  
SS  
V
N/A  
5301 tbl 01  
NOTE:  
1. BW3 and BW4 are not applicable for the IDT71V35781.  
OCTOBER 2000  
1
©2000IntegratedDeviceTechnology,Inc.  
DSC-5301/01  

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