Datasheet > IDT71V35761S166B

IDT71V35761S166B

更新时间： 2024-11-16 09:33:59

品牌	Logo	应用领域
艾迪悌 - IDT		静态存储器
页数	文件大小	规格书
22页	622K
描述
Cache SRAM, 128KX36, 3.5ns, CMOS, PBGA119, BGA-119

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

IDT71V35761S166B 数据手册

128K x 36, 256K x 18

IDT71V35761S

IDT71V35781S

IDT71V35761SA

IDT71V35781SA

3.3VSynchronousSRAMs

3.3VI/O,PipelinedOutputs

BurstCounter,SingleCycleDeselect

Features

Description

◆

128K x 36, 256K x 18 memory configurations

The IDT71V35761/781 are high-speed SRAMs organized as

128Kx36/256Kx18.TheIDT71V35761/781SRAMscontainwrite,data,

addressandcontrolregisters. InternallogicallowstheSRAMtogenerate

aself-timedwritebaseduponadecisionwhichcanbeleftuntiltheendof

thewritecycle.

◆

Supports high system speed:

Commercial:

– 200MHz 3.1ns clock access time

CommercialandIndustrial:

– 183MHz 3.3ns clock access time

– 166MHz 3.5ns clock access time

LBO input selects interleaved or linear burst mode

Theburstmodefeatureoffersthehighestlevelofperformancetothe

systemdesigner,astheIDT71V35761/81canprovidefourcyclesofdata

forasingleaddress presentedtotheSRAM. Aninternalburstaddress

◆

Self-timedwritecyclewithglobalwritecontrol(GW),bytewrite counteracceptsthefirstcycleaddressfromtheprocessor,initiatingthe

enable (BWE), and byte writes (BWx)

3.3V core power supply

Power down controlled by ZZ input

3.3V I/O

accesssequence.Thefirstcycleofoutputdatawillbepipelinedforone

cycle before it is available on the next rising clock edge. If burst mode

operationisselected(ADV=LOW),thesubsequentthreecyclesofoutput

datawillbeavailabletotheuseronthenextthreerisingclockedges. The

◆

Optional - Boundary Scan JTAG Interface (IEEE 1149.1 orderofthesethreeaddressesaredefinedbytheinternalburstcounter

compliant)

andthe LBO inputpin.

◆

Packaged in a JEDEC Standard 100-pin plastic thin quad

TheIDT71V35761/781SRAMsutilizeIDT’slatesthigh-performance

flatpack(TQFP),119ballgridarray(BGA)and165finepitchball CMOSprocessandarepackagedinaJEDECstandard14mmx20mm

grid array

100-pin thinplasticquadflatpack(TQFP)aswellasa119ballgridarray

(BGA) and 165 fine pitch ball grid array.

PinDescriptionSummary

A0-A17

Address Inputs

Input

Output

Input

I/O

Synchronous

Asynchronous

Synchronous

N/A

Chip Enable

, CS

Chip Selects

Output Enable

Global Write Enable

Byte Write Enable

Individual Byte Write Selects

Clock

BWE

BW , BW

(1)

, BW

CLK

Burst Address Advance

Address Status (Cache Controller)

Address Status (Processor)

Linear / Interleaved Burst Order

Test Mode Select

Test Data Input

Synchronous

ADV

ADSC

ADSP

LBO

TMS

TDI

Synchronous

N/A

TCK

TDO

TRST

Test Clock

Test Data Output

Synchronous

Asynchronous

Synchronous

N/A

JTAG Reset (Optional)

Sleep Mode

I/O

-I/O31, I/OP1-I/OP4

DD, VDDQ

Data Input / Output

Core Power, I/O Power

Ground

Supply

N/A

NOTE:

5301 tbl 01

1. BW3 and BW4 are not applicable for the IDT71V35781.

JUNE 2003

DSC-5301/03

12 3 4 5 6 7...22

中文翻译

下载PDF

与IDT71V35761S166B相关器件

型号	品牌	获取价格	描述	数据表
IDT71V35761S166BG	IDT	获取价格	128K x 36, 256K x 18 3.3V Synchronous SRAMs 3.3V I/O, Pipelined Outputs Burst Counter, Sin
IDT71V35761S166BG8	IDT	获取价格	Cache SRAM, 128KX36, 3.5ns, CMOS, PBGA119, BGA-119
IDT71V35761S166BGG	IDT	获取价格	3.3V Synchronous SRAMs 3.3V I/O, Pipelined Outputs Burst Counter, Single Cycle Deselect
IDT71V35761S166BGG8	IDT	获取价格	3.3V Synchronous SRAMs 3.3V I/O, Pipelined Outputs Burst Counter, Single Cycle Deselect
IDT71V35761S166BGGI	IDT	获取价格	3.3V Synchronous SRAMs 3.3V I/O, Pipelined Outputs Burst Counter, Single Cycle Deselect
IDT71V35761S166BGGI8	IDT	获取价格	3.3V Synchronous SRAMs 3.3V I/O, Pipelined Outputs Burst Counter, Single Cycle Deselect
IDT71V35761S166BGI	IDT	获取价格	128K x 36, 256K x 18 3.3V Synchronous SRAMs 3.3V I/O, Pipelined Outputs Burst Counter, Sin
IDT71V35761S166BQ	IDT	获取价格	128K x 36, 256K x 18 3.3V Synchronous SRAMs 3.3V I/O, Pipelined Outputs Burst Counter, Sin
IDT71V35761S166BQ8	IDT	获取价格	Cache SRAM, 128KX36, 3.5ns, CMOS, PBGA165, FBGA-165
IDT71V35761S166BQG	IDT	获取价格	3.3V Synchronous SRAMs 3.3V I/O, Pipelined Outputs Burst Counter, Single Cycle Deselect

与IDT71V35761S166B相关文章

解析光耦仿真器：升级光耦合器技术的必要性
2024-11-18

6
英伟达新一代Blackwell GPU过热问题致交付延迟
2024-11-18

3
国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
2024-11-14

29
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
2024-11-14

12

产品中心

服务支持

精选活动

关于我们

帮助中心

IDT71V35761S166B

IDT71V35761S166B 数据手册

与IDT71V35761S166B相关器件

与IDT71V35761S166B相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

IDT71V35761S166B

IDT71V35761S166B 数据手册

与IDT71V35761S166B相关器件

与IDT71V35761S166B相关文章

您还可以找

您在本页遇到什么问题？