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IDT71V256SA_04 PDF预览

IDT71V256SA_04

更新时间: 2024-11-16 05:28:23
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器
页数 文件大小 规格书
8页 474K
描述
Lower Power 3.3V CMOS Fast SRAM 256K (32K x 8-Bit)

IDT71V256SA_04 数据手册

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Lower Power  
IDT71V256SA  
3.3V CMOS Fast SRAM  
256K (32K x 8-Bit)  
Features  
Description  
Ideal for high-performance processor secondary cache  
Commercial (0°C to +70°C) and Industrial (–40°C to +85°C)  
temperature range options  
TheIDT71V256SAisa 262,144-bithigh-speedstaticRAMorganized  
as32Kx8.ItisfabricatedusingIDT’shigh-performance,high-reliability  
CMOStechnology.  
Fast access times:  
TheIDT71V256SAhasoutstandinglowpowercharacteristicswhile  
at the same time maintaining very high performance. Address access  
times of as fast as 10ns are ideal for 3.3V secondary cache in 3.3V  
desktopdesigns.  
Whenpowermanagementlogicputs the IDT71V256SAinstandby  
mode,itsverylowpowercharacteristicscontributetoextendedbatterylife.  
BytakingCSHIGH,theSRAMwillautomaticallygotoalowpowerstandby  
modeandwillremaininstandbyaslongasCSremainsHIGH.Further-  
more,underfullstandbymode(CSatCMOSlevel,f=0),powerconsump-  
tionisguaranteedtoalwaysbelessthan6.6mWandtypicallywillbemuch  
smaller.  
– CommercialandIndustrial:10/12/15/20ns  
Low standby current (maximum):  
– 2mAfullstandby  
Small packages for space-efficient layouts:  
– 28-pin 300 mil SOJ  
– 28-pin TSOP Type I  
Produced with advanced high-performance CMOS  
technology  
Inputs and outputs are LVTTL-compatible  
Single 3.3V(±0.3V) power supply  
TheIDT71V256SAispackagedina28-pin300milSOJanda28-pin  
300 mil TSOP Type I.  
FunctionalBlockDiagram  
A0  
VCC  
GND  
262,144 BIT  
MEMORY ARRAY  
ADDRESS  
DECODER  
A14  
I/O  
0
I/O CONTROL  
INPUT  
DATA  
CIRCUIT  
I/O7  
,
CS  
OE  
CONTROL  
CIRCUIT  
3101 drw 01  
WE  
JANUARY 2004  
1
DSC-3101/08  
©2004IntegratedDeviceTechnology,Inc.  

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