Datasheet > IDT70V28L

IDT70V28L

更新时间： 2024-09-14 23:05:03

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
17页	153K
描述
HIGH-SPEED 3.3V 64K x 16 DUAL-PORT STATIC RAM

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中文翻译

获取价格

数据手册

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IDT70V28L 数据手册

IDT70V28L

HIGH-SPEED 3.3V

64K x 16 DUAL-PORT

STATIC RAM

ꢀeatures

◆

True Dual-Ported memory cells which allow simultaneous

access of the same memory location

High-speed access

– Commercial:15/20ns (max.)

– Industrial:20ns (max.)

M/S = VIH for BUSY output flag on Master,

M/S = VIL for BUSY input on Slave

Busy and Interrupt Flags

On-chip port arbitration logic

Full on-chip hardware support of semaphore signaling

between ports

◆

Low-power operation

◆

– IDT70V28L

Fully asynchronous operation from either port

Separate upper-byte and lower-byte controls for multi-

plexed bus and bus matching compatibility

LVTTL-compatible, single 3.3V (±0.3V) power supply

Available in a 100-pin TQFP

Active: 440mW (typ.)

Standby: 660µW (typ.)

Dual chip enables allow for depth expansion without

external logic

IDT70V28 easily expands data bus width to 32 bits or

more using the Master/Slave select when cascading more

than one device

◆

Industrial temperature range (–40°C to +85°C) is available

for selected speeds

ꢀunctional Block Diagram

R/WL

UBL

R/WR

UBR

CE0L

CE0R

CE1L

CE1R

OER

LBR

OEL

LBL

I/O ^8-15L

I/O8-15R

I/O

Control

I/O

Control

0-7L

I/O

I/O_0-7R

(1,2)

BUSYR

BUSYL

64Kx16

MEMORY

ARRAY

70V28

15L

A15R

Address

Decoder

Address

Decoder

A0L

A0R

ARBITRATION

INTERRUPT

SEMAPHORE

LOGIC

CE0R

CE0L

CE1L

OEL

CE1R

OER

R/WL

R/WR

SEML

INTL

SEMR

(2)

INTR

M/S⁽¹⁾

NOTES:

4849 drw 01

1. BUSY is an input as a Slave (M/S=V^IL) and an output when it is a Master (M/S=VIH).

2. BUSY and INT are non-tri-state totem-pole outputs (push-pull).

JANUARY 2002

DSC-4849/3

12 3 4 5 6 7...17

中文翻译

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