Datasheet > IDT70V3319

IDT70V3319

更新时间： 2024-11-05 23:01:07

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
23页	347K
描述
HIGH-SPEED 3.3V 256/128K x 18 SYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

IDT70V3319 数据手册

HIGH-SPEED 3.3V

256/128K x 18

IDT70V3319/99S

SYNCHRONOUS

DUAL-PORT STATIC RAM

WITH 3.3V OR 2.5V INTERFACE

Features:

◆

– Data input, address, byte enable and control registers

True Dual-Port memory cells which allow simultaneous

access of the same memory location

High-speed data access

– Self-timedwriteallowsfastcycletime

Separate byte controls for multiplexed bus and bus

matching compatibility

Dual Cycle Deselect (DCD) for Pipelined Output mode

LVTTL- compatible, single 3.3V (±150mV) power supply

for core

LVTTL compatible, selectable 3.3V (±150mV) or 2.5V

(±100mV) power supply for I/Os and control signals on

each port

Industrial temperature range (-40°C to +85°C) is

available at 133MHz.

Available in a 128-pin Thin Quad Flatpack, 208-pin fine

pitch Ball Grid Array, and 256-pin Ball

GridArray

Supports JTAG features compliant to IEEE 1149.1

– Due to limited pin count, JTAG is not supported on the

128-pin TQFP package.

◆

– Commercial: 3.6ns (166MHz)/4.2ns (133MHz) (max.)

– Industrial: 4.2ns (133MHz) (max.)

Selectable Pipelined or Flow-Through output mode

– Due to limited pin count PL/FToption is not supported

on the 128-pin TQFP package. Device is pipelined

outputs only on each port.

Counter enable and repeat features

Dual chip enables allow for depth expansion without

additional logic

◆

Full synchronous operation on both ports

– 6ns cycle time, 166MHz operation (6Gbps bandwidth)

– Fast 3.6ns clock to data out

◆

– 1.7ns setup to clock and 0.5ns hold on all control, data, and

address inputs @ 166MHz

Functional Block Diagram

UBL

UBR

LBL

LBR

FT/PIPE

1b 0b

1a 0a

0a 1a

0b 1b

FT/PIPER

1/0

R/WL

R/WR

CE0L

CE0R

CE1R

CE1L

B B

W W

1/0

Dout0-8_L

Dout9-17_L

Dout0-8_R

Dout9-17_R

OEL

OER

0a 1a

1b 0b 1a 0a

0b 1b

0/1

FT/PIPE

0/1

256K x 18

MEMORY

ARRAY

I/O0R - I/O17R

Din_L

I/O0L - I/O17L

Din_R

CLKR

CLKL

(1)

17L

17R

Counter/

Address

Reg.

Counter/

Address

Reg.

A0L

ADDR_R

ADDR_L

REPEAT

ADS

CNTEN

REPEAT

ADS

CNTEN

5623 tbl 01

TDI

TCK

TMS

TRST

JTAG

NOTE:

1. A17 is a NC for IDT70V3399.

TDO

MAY 2003

DSC 5623/7

12 3 4 5 6 7...23

中文翻译

下载PDF

与IDT70V3319相关器件

型号	品牌	获取价格	描述	数据表
IDT70V3319S133BC	IDT	获取价格	HIGH-SPEED 3.3V 256/128K x 18 SYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE
IDT70V3319S133BC8	IDT	获取价格	Dual-Port SRAM, 256KX18, 15ns, CMOS, PBGA256, 17 X 17 MM, 1.40 MM HEIGHT, 1 MM PITCH, BGA-
IDT70V3319S133BCG	IDT	获取价格	Dual-Port SRAM, 256KX18, 4.2ns, CMOS, CBGA256, 17 X 17 MM X 1.4 MM, 1 MM PITCH, GREEN, BGA
IDT70V3319S133BCGI	IDT	获取价格	Dual-Port SRAM, 256KX18, 4.2ns, CMOS, CBGA256, 17 X 17 MM X 1.4 MM, 1 MM PITCH, GREEN, BGA
IDT70V3319S133BCGI8	IDT	获取价格	Dual-Port SRAM, 256KX18, 15ns, CMOS, PBGA256, BGA-256
IDT70V3319S133BCI	IDT	获取价格	HIGH-SPEED 3.3V 256/128K x 18 SYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE
IDT70V3319S133BF	IDT	获取价格	HIGH-SPEED 3.3V 256/128K x 18 SYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE
IDT70V3319S133BF8	IDT	获取价格	Dual-Port SRAM, 256KX18, 15ns, CMOS, PBGA208, 15 X 15 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, F
IDT70V3319S133BFG	IDT	获取价格	暂无描述
IDT70V3319S133BFGI8	IDT	获取价格	Dual-Port SRAM, 256KX18, 15ns, CMOS, PBGA208, FBGA-208

与IDT70V3319相关文章

英伟达新AI芯片Rubin或提前半年亮相
2024-11-05

14
苹果iPhone 17将全系采用三星/LG显示LTPO OLED面板
2024-11-05

12
三星深化印度制造布局，供应链本地化进程加速
2024-10-29

36
芯擎科技“星辰一号”自动驾驶芯片点亮成功，2025年量产在即
2024-10-29

33

产品中心

服务支持

精选活动

关于我们

帮助中心

IDT70V3319

IDT70V3319 数据手册

与IDT70V3319相关器件

与IDT70V3319相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

IDT70V3319

IDT70V3319 数据手册

与IDT70V3319相关器件

与IDT70V3319相关文章

您还可以找

您在本页遇到什么问题？