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IDT70V3319S166BFI PDF预览

IDT70V3319S166BFI

更新时间: 2024-09-15 23:01:07
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
23页 347K
描述
HIGH-SPEED 3.3V 256/128K x 18 SYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE

IDT70V3319S166BFI 数据手册

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HIGH-SPEED 3.3V  
256/128K x 18  
IDT70V3319/99S  
SYNCHRONOUS  
DUAL-PORT STATIC RAM  
WITH 3.3V OR 2.5V INTERFACE  
Features:  
– Data input, address, byte enable and control registers  
True Dual-Port memory cells which allow simultaneous  
access of the same memory location  
High-speed data access  
– Self-timedwriteallowsfastcycletime  
Separate byte controls for multiplexed bus and bus  
matching compatibility  
Dual Cycle Deselect (DCD) for Pipelined Output mode  
LVTTL- compatible, single 3.3V (±150mV) power supply  
for core  
LVTTL compatible, selectable 3.3V (±150mV) or 2.5V  
(±100mV) power supply for I/Os and control signals on  
each port  
Industrial temperature range (-40°C to +85°C) is  
available at 133MHz.  
Available in a 128-pin Thin Quad Flatpack, 208-pin fine  
pitch Ball Grid Array, and 256-pin Ball  
GridArray  
Supports JTAG features compliant to IEEE 1149.1  
– Due to limited pin count, JTAG is not supported on the  
128-pin TQFP package.  
– Commercial: 3.6ns (166MHz)/4.2ns (133MHz) (max.)  
– Industrial: 4.2ns (133MHz) (max.)  
Selectable Pipelined or Flow-Through output mode  
– Due to limited pin count PL/FToption is not supported  
on the 128-pin TQFP package. Device is pipelined  
outputs only on each port.  
Counter enable and repeat features  
Dual chip enables allow for depth expansion without  
additional logic  
Full synchronous operation on both ports  
– 6ns cycle time, 166MHz operation (6Gbps bandwidth)  
– Fast 3.6ns clock to data out  
– 1.7ns setup to clock and 0.5ns hold on all control, data, and  
address inputs @ 166MHz  
Functional Block Diagram  
UBL  
UBR  
LBL  
LBR  
FT/PIPE  
L
1b 0b  
b
1a 0a  
a
0a 1a  
a
0b 1b  
b
FT/PIPER  
1/0  
1/0  
R/WL  
R/WR  
CE0L  
CE0R  
1
1
CE1R  
CE1L  
B
B
B B  
0
W W  
0
W W  
0
L
1
L
1
0
R
R
1/0  
1/0  
Dout0-8_L  
Dout9-17_L  
Dout0-8_R  
Dout9-17_R  
OEL  
OER  
,
0a 1a  
1b 0b 1a 0a  
ab  
0b 1b  
ba  
0/1  
FT/PIPE  
R
FT/PIPE  
L
0/1  
256K x 18  
MEMORY  
ARRAY  
I/O0R - I/O17R  
Din_L  
I/O0L - I/O17L  
Din_R  
,
CLKR  
CLKL  
(1)  
L
(1)  
A
17L  
A
A
17R  
0R  
Counter/  
Address  
Reg.  
Counter/  
Address  
Reg.  
A0L  
ADDR_R  
ADDR_L  
REPEAT  
ADS  
CNTEN  
REPEAT  
ADS  
CNTEN  
R
R
L
R
L
5623 tbl 01  
TDI  
TCK  
TMS  
TRST  
JTAG  
NOTE:  
1. A17 is a NC for IDT70V3399.  
TDO  
MAY 2003  
1
DSC 5623/7  
©2003 Integrated DeviceTechnology,Inc.  

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