IDT5T93GL06

更新时间： 2024-11-11 02:59:23

品牌	Logo	应用领域
艾迪悌 - IDT		时钟
页数	文件大小	规格书
15页	108K
描述
2.5V LVDS 1:6 GLITCHLESS CLOCK BUFFER TERABUFFER-TM II

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

IDT5T93GL06 数据手册

IDT5T93GL06

INDUSTRIALTEMPERATURERANGE

2.5VLVDS1:6GLITCHLESSCLOCKBUFFERTERABUFFERII

2.5V LVDS 1:6 GLITCHLESS

IDT5T93GL06

CLOCK BUFFER

TERABUFFER™ II

DESCRIPTION:

FEATURES:

TheIDT5T93GL062.5Vdifferentialclockbufferisauser-selectablediffer-

• Guaranteed Low Skew < 25ps (max)

• Very low duty cycle distortion < 100ps (max)

• High speed propagation delay < 2ns (max)

• Up to 800MHz operation

entialinputtosixLVDSoutputs. ThefanoutfromadifferentialinputtosixLVDS

outputsreducesloadingontheprecedingdriverandprovidesanefficientclock

distributionnetwork. TheIDT5T93GL06canactasatranslatorfromadifferential

HSTL, eHSTL, LVEPECL (2.5V), LVPECL (3.3V), CML, or LVDS input to

LVDS outputs. A single-ended 3.3V / 2.5V LVTTL input can also be used to

translatetoLVDSoutputs. Theredundantinputcapabilityallowsforaglitchless

change-over from a primary clock source to a secondary clock source up to

650MHz. SelectableinputsarecontrolledbySEL. Duringtheswitchover,the

outputwilldisablelowforuptothreeclockcyclesofthepreviously-selectedinput

clock. The outputs will remain low for up to three clock cycles of the newly-

selectedclock,afterwhichtheoutputswillstartfromthenewly-selectedinput.

AFSELpinhasbeenimplementedtocontroltheswitchoverincaseswherea

clocksourceisabsentorisdriventoDClevelsbelowtheminimumspecifications.

The IDT5T93GL06 outputs can be asynchronously enabled/disabled.

Whendisabled,theoutputswilldrivetothevalueselectedbytheGLpin. Multiple

power and grounds reduce noise.

• Glitchless input clock switching up to 650MHz

• Selectable inputs

• Hot insertable and over-voltage tolerant inputs

• 3.3V / 2.5V LVTTL, HSTL, eHSTL, LVEPECL (2.5V), LVPECL (3.3V),

CML, or LVDS input interface

• Selectable differential inputs to six LVDS outputs

• Power-down mode

• 2.5V VDD

• Available in VFQFPN package

APPLICATIONS:

• Clock distribution

FUNCTIONALBLOCKDIAGRAM

OUTPUT

CONTROL

OUTPUT

CONTROL

OUTPUT

CONTROL

OUTPUT

CONTROL

OUTPUT

CONTROL

SEL

FSEL

OUTPUT

CONTROL

TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.

INDUSTRIAL TEMPERATURE RANGE

OCTOBER 2003

DSC-6183/8

12 3 4 5 6 7...15

中文翻译

下载PDF

与IDT5T93GL06相关器件

型号	品牌	获取价格	描述	数据表
IDT5T93GL061	IDT	获取价格	2.5V LVDS 1:6 GLITCHLESS CLOCK BUFFER TERABUF
IDT5T93GL061PFGI	IDT	获取价格	2.5V LVDS 1:6 GLITCHLESS CLOCK BUFFER TERABUF
IDT5T93GL061PFGI8	IDT	获取价格	Low Skew Clock Driver, 5T Series, 6 True Output(s), 0 Inverted Output(s), PQFP32, GREEN, T
IDT5T93GL061PFI	IDT	获取价格	2.5V LVDS 1:6 GLITCHLESS CLOCK BUFFER TERABUF
IDT5T93GL06NLGI	IDT	获取价格	暂无描述
IDT5T93GL06NLI	IDT	获取价格	2.5V LVDS 1:6 GLITCHLESS CLOCK BUFFER TERABUFFER-TM II
IDT5T93GL06NLI8	IDT	获取价格	Low Skew Clock Driver, 5T Series, 6 True Output(s), 0 Inverted Output(s), PQCC28, PLASTIC,
IDT5T93GL06PFI	IDT	获取价格	Low Skew Clock Driver, 6 True Output(s), 0 Inverted Output(s), PQFP32, TQFP-32
IDT5T93GL10	IDT	获取价格	2.5V LVDS 1:10 GLITCHLESS CLOCK BUFFER TERABU
IDT5T93GL10NLGI	IDT	获取价格	2.5V LVDS 1:10 GLITCHLESS CLOCK BUFFER TERABU

与IDT5T93GL06相关文章

国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
2024-11-14

23
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
2024-11-14

7
AMD宣布全球裁员约1000人，调整战略聚焦增长
2024-11-14

8
英伟达新AI芯片Rubin或提前半年亮相
2024-11-05

31

产品中心

服务支持

精选活动

关于我们

帮助中心

IDT5T93GL06

IDT5T93GL06 数据手册

与IDT5T93GL06相关器件

与IDT5T93GL06相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

IDT5T93GL06

IDT5T93GL06 数据手册

与IDT5T93GL06相关器件

与IDT5T93GL06相关文章

您还可以找

您在本页遇到什么问题？