IDT5T93GL061PFGI

更新时间： 2024-02-03 20:32:27

品牌	Logo	应用领域
艾迪悌 - IDT		时钟
页数	文件大小	规格书
14页	148K
描述
2.5V LVDS 1:6 GLITCHLESS CLOCK BUFFER TERABUFFER⑩ II

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数据手册
替代型号

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IDT5T93GL061PFGI 数据手册

IDT5T93GL061

INDUSTRIALTEMPERATURERANGE

2.5VLVDS1:6GLITCHLESSCLOCKBUFFERTERABUFFERII

2.5V LVDS 1:6 GLITCHLESS

IDT5T93GL061

CLOCK BUFFER

TERABUFFER™ II

DESCRIPTION:

FEATURES:

The IDT5T93GL061 2.5V differential clock buffer is a user-selectable

• Guaranteed Low Skew < 50ps (max)

• Very low duty cycle distortion < 100ps (max)

• High speed propagation delay < 2.2ns (max)

• Up to 450MHz operation

differentialinputtosixLVDSoutputs. Thefanoutfromadifferentialinputtosix

LVDSoutputsreducesloadingontheprecedingdriverandprovidesanefficient

clockdistributionnetwork. TheIDT5T93GL061canactasatranslatorfroma

differentialHSTL,eHSTL,LVEPECL (2.5V),LVPECL(3.3V),CML,orLVDS

input to LVDS outputs. A single-ended 3.3V / 2.5V LVTTL input can also be

usedtotranslatetoLVDSoutputs. Theredundantinputcapabilityallowsfora

glitchlesschange-over fromaprimaryclocksourcetoasecondaryclocksource

upto450MHz. SelectableinputsarecontrolledbySEL. Duringtheswitchover,

theoutputwilldisablelowforuptothreeclockcyclesofthepreviously-selected

inputclock. Theoutputswillremainlowforuptothreeclockcyclesofthenewly-

selectedclock,afterwhichtheoutputswillstartfromthenewly-selectedinput.

AFSELpinhasbeenimplementedtocontroltheswitchoverincaseswherea

clocksourceisabsentorisdriventoDClevelsbelowtheminimumspecifications.

The IDT5T93GL061 outputs can be asynchronously enabled/disabled.

Whendisabled,theoutputswilldrivetothevalueselectedbytheGLpin. Multiple

power and grounds reduce noise.

• Selectable inputs

• Hot insertable and over-voltage tolerant inputs

• 3.3V / 2.5V LVTTL, HSTL, eHSTL, LVEPECL (2.5V), LVPECL (3.3V),

CML, or LVDS input interface

• Selectable differential inputs to six LVDS outputs

• Power-down mode

• 2.5V VDD

• Available in TQFP package

APPLICATIONS:

• Clock distribution

FUNCTIONALBLOCKDIAGRAM

OUTPUT

CONTROL

OUTPUT

CONTROL

OUTPUT

CONTROL

OUTPUT

CONTROL

OUTPUT

CONTROL

SEL

FSEL

OUTPUT

CONTROL

TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.

INDUSTRIAL TEMPERATURE RANGE

JANUARY 2007

DSC 6740/7

12 3 4 5 6 7...14

中文翻译

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IDT5T93GL061PFGI 替代型号

型号	品牌	替代类型	描述	数据表
5T93GL061PFGI8	IDT	类似代替	Low Skew Clock Driver, 5T Series, 6 True Output(s), 0 Inverted Output(s), PQFP32, GREEN, T
5T93GL061PFGI	IDT	类似代替	Low Skew Clock Driver, 5T Series, 6 True Output(s), 0 Inverted Output(s), PQFP32, GREEN, T
IDT5T93GL061PFGI8	IDT	功能相似	Low Skew Clock Driver, 5T Series, 6 True Output(s), 0 Inverted Output(s), PQFP32, GREEN, T

与IDT5T93GL061PFGI相关器件

型号	品牌	获取价格	描述	数据表
IDT5T93GL061PFGI8	IDT	获取价格	Low Skew Clock Driver, 5T Series, 6 True Output(s), 0 Inverted Output(s), PQFP32, GREEN, T
IDT5T93GL061PFI	IDT	获取价格	2.5V LVDS 1:6 GLITCHLESS CLOCK BUFFER TERABUF
IDT5T93GL06NLGI	IDT	获取价格	暂无描述
IDT5T93GL06NLI	IDT	获取价格	2.5V LVDS 1:6 GLITCHLESS CLOCK BUFFER TERABUFFER-TM II
IDT5T93GL06NLI8	IDT	获取价格	Low Skew Clock Driver, 5T Series, 6 True Output(s), 0 Inverted Output(s), PQCC28, PLASTIC,
IDT5T93GL06PFI	IDT	获取价格	Low Skew Clock Driver, 6 True Output(s), 0 Inverted Output(s), PQFP32, TQFP-32
IDT5T93GL10	IDT	获取价格	2.5V LVDS 1:10 GLITCHLESS CLOCK BUFFER TERABU
IDT5T93GL10NLGI	IDT	获取价格	2.5V LVDS 1:10 GLITCHLESS CLOCK BUFFER TERABU
IDT5T93GL10NLI	IDT	获取价格	2.5V LVDS 1:10 GLITCHLESS CLOCK BUFFER TERABU
IDT5T93GL10NLI8	IDT	获取价格	Low Skew Clock Driver, 5T Series, 10 True Output(s), 0 Inverted Output(s), PQCC40, PLASTIC

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