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IDT5T93GL04PGGI PDF预览

IDT5T93GL04PGGI

更新时间: 2024-11-11 02:59:23
品牌 Logo 应用领域
艾迪悌 - IDT 时钟驱动器逻辑集成电路光电二极管
页数 文件大小 规格书
17页 754K
描述
2.5V LVDS, 1:4 GLITCHLESS CLOCK BUFFER TERABUFFERII

IDT5T93GL04PGGI 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Obsolete零件包装代码:TSSOP
包装说明:TSSOP, TSSOP24,.25针数:24
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.84
Is Samacsys:N系列:5T
输入调节:DIFFERENTIAL MUXJESD-30 代码:R-PDSO-G24
JESD-609代码:e3长度:7.8 mm
逻辑集成电路类型:LOW SKEW CLOCK DRIVER湿度敏感等级:1
功能数量:1反相输出次数:
端子数量:24实输出次数:4
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP24,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):260
电源:2.5 VProp。Delay @ Nom-Sup:2.2 ns
传播延迟(tpd):2.2 ns认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.05 ns座面最大高度:1.2 mm
子类别:Clock Drivers最大供电电压 (Vsup):2.7 V
最小供电电压 (Vsup):2.3 V标称供电电压 (Vsup):2.5 V
表面贴装:YES温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn) - annealed端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:4.4 mm
最小 fmax:450 MHzBase Number Matches:1

IDT5T93GL04PGGI 数据手册

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2.5V LVDS, 1:4 GLITCHLESS CLOCK BUFFER  
TERABUFFER™ II  
IDT5T93GL04  
General Description  
Features  
The IDT5T93GL04 2.5V differential clock buffer is a  
Guaranteed low skew: <50ps (maximum)  
user-selectable differential input to four LVDS outputs. The fanout  
from a differential input to four LVDS outputs reduces loading on  
the preceding driver and provides an efficient clock distribution  
network. The IDT5T93GL04 can act as a translator from a  
differential HSTL, eHSTL, LVEPECL (2.5V), LVPECL (3.3V),  
CML, or LVDS input to LVDS outputs. A single-ended 3.3V / 2.5V  
LVTTL input can also be used to translate to LVDS outputs. The  
redundant input capability allows for a glitchless change-over from  
a primary clock source to a secondary clock source up to 450MHz.  
Selectable inputs are controlled by SEL. During the switchover,  
the output will disable low for up to three clock cycles of the  
previously-selected input clock. The outputs will remain low for up  
to three clock cycles of the newly-selected clock, after which the  
outputs will start from the newly-selected input. A FSEL pin has  
been implemented to control the switchover in cases where a  
clock source is absent or is driven to DC levels below the minimum  
specifications.  
Very low duty cycle distortion: <100ps (maximum  
High speed propagation delay: <2.2ns (maximum)  
Up to 450MHz operation  
Selectable inputs  
Hot insertable and over-voltage tolerant inputs  
3.3V/2.5V LVTTL, HSTL, eHSTL, LVEPECL (2.5V), LVPECL  
(3.3V), CML or LVDS input interface  
Selectable differential inputs to four LVDS outputs  
Power-down mode  
At power-up, FSEL should be LOW  
2.5V VDD  
-40°C to 85°C ambient operating temperature  
Available in TSSOP package  
The IDT5T9304 outputs can be asynchronously enabled/disabled.  
When disabled, the outputs will drive to the value selected by the  
GL pin. Multiple power and grounds reduce noise.  
Applications  
Clock distribution  
Pin Assignment  
A2  
A2  
GND  
PD  
1
2
24  
23  
GND  
VDD  
FSEL  
VDD  
3
4
22  
21  
5
6
7
8
20  
19  
18  
17  
Q3  
Q3  
Q4  
Q1  
Q1  
Q2  
Q4  
Q2  
VDD  
SEL  
G
VDD  
GL  
A1  
9
16  
15  
14  
13  
10  
11  
12  
GND  
A1  
24-Lead TSSOP  
4.4mm x 7.8mm x 1.0mm package body  
G Package  
Top View  
IDT™ LVDS GLITCHLESS CLOCK BUFFER TERABUFFER™ II  
1
IDT5T93GL04 REV. AJULY 10, 2007  

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