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ICS9222-YG01LF-T PDF预览

ICS9222-YG01LF-T

更新时间： 2024-11-11 14:51:23
品牌 Logo 应用领域
艾迪悌 - IDT 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
6页 93K
描述
PLL Based Clock Driver, 9222 Series, 2 True Output(s), 2 Inverted Output(s), PDSO28, 4.40 MM, 0.65 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-28

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中文翻译

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ICS9222-YG01LF-T 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Transferred零件包装代码：TSSOP
包装说明：TSSOP,针数：28
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.41Is Samacsys：N
系列：9222输入调节：STANDARD
JESD-30 代码：R-PDSO-G28JESD-609代码：e3
长度：9.7 mm逻辑集成电路类型：PLL BASED CLOCK DRIVER
功能数量：1反相输出次数：2
端子数量：28实输出次数：2
最高工作温度：70 °C最低工作温度：
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度（摄氏度）：NOT SPECIFIED
认证状态：Not Qualified座面最大高度：1.2 mm
最大供电电压 (Vsup)：3.465 V最小供电电压 (Vsup)：3.135 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
温度等级：COMMERCIAL端子面层：MATTE TIN
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：4.4 mmBase Number Matches：1

ICS9222-YG01LF-T 数据手册

 浏览型号ICS9222-YG01LF-T的Datasheet PDF文件第2页浏览型号ICS9222-YG01LF-T的Datasheet PDF文件第3页浏览型号ICS9222-YG01LF-T的Datasheet PDF文件第4页浏览型号ICS9222-YG01LF-T的Datasheet PDF文件第5页浏览型号ICS9222-YG01LF-T的Datasheet PDF文件第6页 
Integrated  
Circuit  
Systems, Inc.  
ICS9222-01  
Dual Memory Clock Generator  
General Description  
Features  
•
•
Compatible with all Direct Rambus™ based ICs  
The ICS9222-01 is a High-speed clock generator providing  
two channels up to 450 MHz differential clock source for  
direct Rambus_memory system. It includes two independent  
DDLL’s (Distributed Delay locked loop) and phase detection  
mechanisms to synchronize eachdirect Rambus_ channel  
clock to an external system clock. ICS9222-01 provides a  
solution for a broad range of Direct Rambus memory  
applications. The device works in conjunction with the  
ICS964S101, as well as 9250-22 and others (depending on  
chipset).  
Up to 450 MHz differential clock source for direct  
Rambus™ memory system  
Cycle to cycle jitter is less than 100 ps  
3.3 ± 5% supply  
•
•
•
Synchronization flexibility: Supports systems that need  
clock domains of Rambus channel to synchronize with  
system or processor clock, or systems that do not  
require synchronization of the Rambus clock to another  
system clock.  
The ICS9222-01 power management support system turns  
“off” the Rambus channel clock to minimize power  
consumption for mobile and other power sensitive  
applications. In “clock off” mode the device remains “on”  
while the output is disabled, allowing fast transitions between  
clock-off and clock–on states. In “power down” mode it  
completely powers down for minimum power dissipation.  
•
•
Excellent power management support  
REFCLK input is from the main clock generator such as  
a 9250-22.  
Pin Configuration  
Block Diagram  
CLK_STOP#  
PD#  
VDDREF  
REFCLK  
VDDC  
SYNCLK0  
PCLK0  
GND  
VDDP  
GND  
SYNCLK1  
PCLK1  
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
FS0  
FS1  
FS2  
GND  
CLKB0  
CLK0  
VDDCLK  
VDDCLK  
CLK1  
CLKB1  
GND  
MULT_0  
MULT_1  
MULT_2  
Test MUX  
FS (2:0)  
Bypass MUX  
Bypclk  
GND  
PLLclk  
PCLK1  
SYNCLK1  
Phase  
Detector  
CLK1  
Phase  
Aligner  
CLKB1  
REFCLK  
B
A
GND  
PLL  
VDDC  
CLK0  
Phase  
Aligner  
CLKB0  
VDDIPD  
CLK_STOP#  
PD#  
MULT (2:0)  
2
Phase  
Detector  
GND  
PAclk  
PCLK0  
SYNCLK0  
28-Pin TSSOP  
0274C—11/14/05  
123456

中文翻译

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