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ICS9248-107 PDF预览

ICS9248-107

更新时间: 2024-11-10 22:11:03
品牌 Logo 应用领域
矽成 - ICSI /
页数 文件大小 规格书
14页 142K
描述
Frequency Timing Generator for PENTIUM II Systems

ICS9248-107 数据手册

 浏览型号ICS9248-107的Datasheet PDF文件第2页浏览型号ICS9248-107的Datasheet PDF文件第3页浏览型号ICS9248-107的Datasheet PDF文件第4页浏览型号ICS9248-107的Datasheet PDF文件第5页浏览型号ICS9248-107的Datasheet PDF文件第6页浏览型号ICS9248-107的Datasheet PDF文件第7页 
Integrated  
Circuit  
Systems, Inc.  
ICS9248-107  
Frequency Timing Generator for PENTIUM II Systems  
RecommendedApplication:  
Pin Configuration  
RCC chipset  
GNDREF  
REF0  
*SEL24_48#/REF1  
VDDREF  
X1  
1
2
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
VDDLAPIC  
IOAPIC0  
IOAPIC1  
GNDLAPIC  
IOAPIC2  
VDDLCPU  
CPUCLK0  
GNDLCPU  
CPUCLK1  
VDDLCPU  
CPUCLK2  
CPUCLK3  
GNDLCPU  
VDD66  
OutputFeatures:  
3
4
5
6
7
8
9
4 - CPUs @ 2.5V, up to 180MHz.  
X2  
GNDPCI  
3-IOAPIC@2.5V  
3-3V66MHz@3.3V.  
11-PCIs@3.3V  
*FS0/PCICLK_F  
*FS1/PCICLK1  
VDDPCI  
*FS2/PCICLK2  
*FS3/PCICLK3  
GNDPCI  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
1-48MHz,@3.3Vfixed  
1-24/48MHz,@3.3V  
PCICLK4  
PCICLK5  
VDDPCI  
PCICLK6  
PCICLK7  
GNDPCI  
PCICLK8  
PCICLK9  
PCICLK10  
VDDPCI  
3V66_0  
3V66_1  
3V66_2  
GND66  
SDATA  
SCLK  
VDD48  
48MHz/FS4*  
24_48MHz  
GND48  
Features:  
Up to 180MHz frequency support  
I2  
C
{
Use a zero delay buffer such as the ICS9179-06 to  
generate SDRAM clocks.  
PD#  
Support power management: Power down Mode  
fromI2Cprogramming.  
48-pin SSOP  
*120K ohm pull-up to VDD on indicated inputs.  
Spread spectrum for EMI control  
± 0.25% center spread).  
Usesexternal14.318MHzcrystal  
5 - FS pins for frequency select  
KeySpecifications:  
CPU Output Jitter: <250ps  
IOAPIC Output Jitter: <500ps  
Block Diagram  
48MHz, 3V66, PCIOutputJitter:<500ps  
Ref Output Jitter. <1000ps  
PLL2  
48MHz  
CPUOutputSkew:<175ps  
24_48MHz  
/ 2  
IOAPIC Output Skew <250ps  
X1  
X2  
XTAL  
OSC  
REF(1:0)  
PCIOutputSkew:<580ps  
3V66OutputSkew<250ps  
PLL1  
Spread  
CPU  
DIVDER  
CPUCLK (3:0)  
IOAPIC (2:0)  
CPU to 3V66 Output Offset: 0.8 - 1.8ns (typ = 1.3ns)  
CPU to PCI Output Offset: 0.0 - 1.5ns (typ = 1.0ns)  
CPU to IOAPIC Output Offset: 1.5 - 4.0ns (typ = 2.0ns)  
Spectrum  
IOAPIC  
DIVDER  
SEL24_48#  
SDATA  
PCI  
DIVDER  
Control  
Logic  
PCICLK (10:0)  
PCICLK_F  
I2C  
{
SCLK  
FS(4:0)  
Config.  
Reg.  
3V66  
DIVDER  
3V66 (2:0)  
PD#  
ICS reserves the right to make changes in the device data identified in  
this publication without further notice. ICS advises its customers to  
obtain the latest version of all device data to verify that any  
9248-107RevA -5/21/01  
information being relied upon by the customer is current and accurate.  

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