Integrated
Circuit
Systems, Inc.
ICS9248-128
Frequency Generator & Integrated Buffers
RecommendedApplication:
SIS 530/620 style chipset
Pin Configuration
VDDR/X
*MODE/REF0
GNDREF
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VDDLAPIC
IOAPIC
Output Features:
•
•
•
•
•
•
•
- 3 CPU @ 2.5V/3.3V up to 133.3 MHz.
- 6 PCI @ 3.3V (including 1 free-running)
- 13 SDRAMs @ 3.3V up to 133.3MHz.
- 3 REF @ 3.3V, 14.318MHz
REF1/SD_SEL#*
GNDLAPIC
REF2/CPU2.5_3.3#*
CPUCLK1
VDDLCPU
CPUCLK2
CPUCLK3
GNDCPU
SDRAM0
SDRAM1
VDDSDR
SDRAM2
SDRAM3
GNDSDR
SDRAM4
SDRAM5
VDDSDR
SDRAM6
SDRAM7
GNDSDR
X1
X2
VDDPCI
*FS1/PCICLK_F
*FS2.PCICLK0
GNDPCI
PCICLK1
PCICLK2
PCICLK3
PCICLK4
VDDPCI
SDRAM12
GNDSDR
- 1 clock @ 24/14.3 MHz selectable output for SIO
- 1 Fixed clock at 48MHz (3.3V)
- 1 IOAPIC @ 2.5V / 3.3V
Features:
*CPU_STOP# /SDRAM11
*PCI_STOP# /SDRAM10
VDDSD/C
*SDRAM_STOP# /SDRAM9
*PD# /SDRAM8
GNDFIX
•
•
Up to 133MHz frequency support
Support power management: CPU, PCI, SDRAM stop and
Power down Mode from I2C programming.
•
Spread spectrum for EMI control ( ± 0.25% center spread
& 0 to -0.5% down spread).
SDATA
SCLK
48MHz/FS0*
SIO/SEL24_14#MHz
*
•
•
Uses external 14.318MHz crystal
FS pins for frequency select
48-Pin SSOP
* Internal Pull-up Resistor of
120K to 3.3V on indicated inputs
Key Specifications:
•
•
CPU – CPU<175ps
SDRAM – SDRAM < 350ps
•
•
•
CPU–SDRAM < 500ps
CPU(early) – PCI : 1-4ns (typ. 2ns)
PCI – PCI <500ps
Block Diagram
Functionality
CPU SDRAM
PCI
MHZ
SD_SEL FS2 FS1 FS0
PLL2
48MHz
SIO
MHZ
MHZ
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
90.00
90.00
30.00
/2
66.70 100.05 33.35
SEL24_14#
95.00
63.33
31.66
33.33
30.00
37.33
31.00
32.33
33.35
30.00
33.32
31.66
X1
X2
XTAL
OSC
100.00 66.66
100.00 75.00
112.00 74.66
124.00 82.66
REF(2:0)
IOAPIC
3
PLL1
Spread
Spectrum
STOP
CPUCLK (3:1)
SDRAM (12:0)
3
13
5
97.00
66.70
75.00
83.30
95.00
97.00
66.70
75.00
83.30
95.00
CPU_STOP
MODE
FS(2:0)
CPU3.3#_2.5
SD_SEL#
LATCH
3
PCI
CLOCK
DIVDER
STOP
PCICLK (4:0)
PCICLK_F
5
POR
SDRAM_STOP#
CPU_STOP#
PCI_STOP#
PD#
PCI_STOP
100.00 100.00 33.33
112.00 112.00 37.33
124.00 124.00 31.00
133.30 133.30 33.33
Control
Logic
Config.
Reg.
SDATA
SCLK
Note: REF, IOAPIC = 14.318MHz
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
9248-128 Rev B 11/16/00
Third party brands and names are the property of their respective owners.
information being relied upon by the customer is current and accurate.