Datasheet > ICS9220YGLF-T

ICS9220YGLF-T

更新时间： 2024-11-11 21:11:15

品牌	Logo	应用领域
艾迪悌 - IDT		光电二极管外围集成电路
页数	文件大小	规格书
17页	210K
描述
Processor Specific Clock Generator, PDSO28, 4.40 MM, 0.65 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-28

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ICS9220YGLF-T 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	TSSOP
包装说明：	4.40 MM, 0.65 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-28	针数：	28
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.84
JESD-30 代码：	R-PDSO-G28	JESD-609代码：	e3
长度：	9.7 mm	端子数量：	28
最高工作温度：	70 °C	最低工作温度：
封装主体材料：	PLASTIC/EPOXY	封装代码：	TSSOP
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：	260	认证状态：	Not Qualified
座面最大高度：	1.2 mm	最大供电电压：	2.625 V
最小供电电压：	2.375 V	标称供电电压：	2.5 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	MATTE TIN
端子形式：	GULL WING	端子节距：	0.65 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	30
宽度：	4.4 mm	uPs/uCs/外围集成电路类型：	CLOCK GENERATOR, PROCESSOR SPECIFIC
Base Number Matches：	1

ICS9220YGLF-T 数据手册

ICS9220

Integrated

Circuit

Systems, Inc.

Programmable Rambus^TMXDR^TMClock Generator

General Description

Features

•

300 - 700 MHz clock source

2 open-drain differential output drives with short

term jitter < 40ps

Spread spectrum compatible

Reference clock is differential or single-ended

100MHz

SMBus programmability for:

- frequency multiplier

- output enable

- operating mode

Support systems where XDR subsystem is

asynchronous to other system clocks

The ICS9220 clock generator provides Programmable

clock signals to support the Rambus XDR^TMmemory

subsystem and Redwood logic interface. The ICS9220

has been optimized for 100MHz reference input that may

or may not be modulated for spread spectrum. The

ICS9220 provides 2 differential clock pairs in a space

saving 28-pin TSSOP package and provides an off-the-

shelf high-performance interface solution.

•

Figure 1 shows the major components of the ICS9220

XDR Clock Generator. These include the a PLL, a Bypass

Multiplexer and two differential output buffers. The outputs

can be disabled by a logic low on the OE pin. An output

is enabled by the combination of the OE pin being high,

and 1 in its SMBus Output control register bit.

•

2.5V power supply

The PLL receives a reference clock, CLK_INT/C and

outputs a clock signal at a frequency equal to the input

frequency times a multiplier. Table 2 shows the multipliers

selectable via the SMBus interface. This clock signal is

then fed to the differential output buffers to drive the

enabled clocks. Disabled outputs are set to Hi-Z. The

Bypass mode routes the input clock, CLK_INT/C, directly

to the differential output buffers, bypassing the PLL.

Up to four ICS9220 devices can be cascaded on the same

SMBus. Table 3 shows the SMBus addressing and control

for the four devices.

Block Diagram

Pin Configuration

AVDD2.5

AGND

28 VDD2.5

27 GND

26 GND

25 ODCLK_T0

24 ODCLK_C0

23 GND

22 VDD2.5

21 VDD2.5

20 GND

RegA

IREFY

AGND

CLK_INT

CLK_INC

VDD2.5

GND

SMBCLK

SMBDAT 10

OE 11

ODCLK_T0

BYPASS#/PLL

ODCLK_C0

Bypass

MUX

RegB

ODCLK_T1

ODCLK_C1

CLK_INT

CLK_INC

PLL

SMBCLK

19 ODCLK_T1

18 ODCLK_C1

17 GND

SMBDAT

AS1

AS2

AS1 12

AS2 13

16 GND

BYPASS#/PLL 14

15 VDD2.5

28-Pin 4.4mm TSSOP

1227G—11/05/07

XDR is a trademark of Rambus

12 3 4 5 6 7...17

中文翻译

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与ICS9220YGLF-T相关器件

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ICS9248-101	ICSI	获取价格	Frequency Generator & Integrated Buffers for PENTIUM/ProTM & K6
ICS9248-103	ICSI	获取价格	Frequency Generator & Integrated Buffers for PENTIUM/ProTM
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