62.5MHZ TO 250MHZ, 1:4 LVCMOS/
LVTTL ZERO DELAY CLOCK BUFFER
ICS86004-01
FEATURES
GENERAL DESCRIPTION
• Four LVCMOS/LVTTL outputs, 7Ω typical output impedance
• Single LVCMOS/LVTTL clock input
The ICS86004-01 is a high performance 1-to-4
ICS
HiPerClockS™
LVCMOS/LVTTL Clock Buffer and a member of
the HiPerClockS™ family of High Performance
Clock Solutions from IDT. The ICS86004-01 has a
fully integrated PLL and can be configured as zero
• CLK accepts the following input levels: LVCMOS or LVTTL
• Output frequency range: 62.5MHz to 250MHz
• Input frequency range: 62.5MHz to 250MHz
delay buffer and has an input and output frequency range of
62.5MHz to 250MHz. The external feedback allows the
device to achieve “zero delay” between the input clock and the
output clocks. The PLL_SEL pin can be used to bypass the
PLL for system test and debug purposes. In bypass mode, the
reference clock is routed around the PLL and into the
internal output divider.
• External feedback for “zero delay” clock regeneration
with configurable frequencies
• Fully integrated PLL
• Cycle-to-cycle jitter, (F_SEL = 1): 45ps (maximum)
• Output skew: 60ps (maximum)
• Supply Voltage Modes:
(Core/Output)
3.3V/3.3V
3.3V/2.5V
2.5V/2.5V
• 5V tolerant input
• -40°C to 70°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
CONTROL INPUT FUNCTION TABLE
Input/Output
Input
Frequency Range (MHz)
F_SEL
Minimum
125
Maximum
250
0
1
62.5
125
BLOCK DIAGRAM
PIN ASSIGNMENT
PLL_SEL
1
2
3
4
5
6
7
8
Q1
GND
Q0
F_SEL
VDD
CLK
GND
VDDA
16
15
14
13
12
11
10
9
VDDO
Q2
GND
Q3
VDDO
MR
FB_IN
PLL_SEL
Q0
Q1
Q2
Q3
÷8
0
1
CLK
PLL
1:1
FB_IN
ICS86004-01
16-Lead TSSOP
4.4mm x 5.0mm x 0.92mm package body
G Package
Top View
MR
F_SEL
IDT™ / ICS™ LVCMOS ZERO DELAY CLOCK BUFFER
1
ICS86004BG-01 REV C NOVEMBER 30, 2006