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ICS503MT

更新时间: 2024-11-01 20:32:43
品牌 Logo 应用领域
艾迪悌 - IDT 时钟光电二极管外围集成电路晶体
页数 文件大小 规格书
7页 131K
描述
Clock Generator, 160MHz, CMOS, PDSO8, 0.150 INCH, SOIC-8

ICS503MT 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:0.150 INCH, SOIC-8针数:8
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.81
Is Samacsys:N其他特性:ALSO OPERATES AT 3 V MINIMUM SUPPLY
JESD-30 代码:R-PDSO-G8JESD-609代码:e0
长度:4.9 mm端子数量:8
最高工作温度:70 °C最低工作温度:
最大输出时钟频率:160 MHz封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP8,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):NOT SPECIFIED电源:3.3/5 V
主时钟/晶体标称频率:50 MHz认证状态:Not Qualified
座面最大高度:1.75 mm子类别:Clock Generators
最大供电电压:5.5 V最小供电电压:4.5 V
标称供电电压:5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:3.9 mm
uPs/uCs/外围集成电路类型:CLOCK GENERATOR, OTHERBase Number Matches:1

ICS503MT 数据手册

 浏览型号ICS503MT的Datasheet PDF文件第2页浏览型号ICS503MT的Datasheet PDF文件第3页浏览型号ICS503MT的Datasheet PDF文件第4页浏览型号ICS503MT的Datasheet PDF文件第5页浏览型号ICS503MT的Datasheet PDF文件第6页浏览型号ICS503MT的Datasheet PDF文件第7页 
DATASHEET  
LOCO™ PLL CLOCK MULTIPLIER  
ICS503  
Description  
Features  
TM  
The ICS503 is a member of the LOCO family, the  
Packaged as 8-pin SOIC (Pb-free) or die  
IDT’s lowest cost PLL clock  
most cost effective way to generate a high-quality, high  
frequency clock output from a lower frequency crystal  
or clock input. The name LOCO stands for Low Cost  
Oscillator, as it is designed to replace crystal oscillators  
in most electronic systems. Using Phase-Locked-Loop  
(PLL) techniques, the device uses a standard  
fundamental mode, inexpensive crystal to produce  
output clocks up to 160 MHz.  
Generates 16.9344 MHz for stereo codecs from the  
14.31818 MHz motherboard clock.  
Can be cost effective in replacing a single  
surface-mount crystal  
Can be driven by other 5xx series  
Input crystal frequency of 5 - 27 MHz  
Input clock frequency of 2 - 50 MHz  
Output clock frequencies up to 160 MHz  
Low jitter - 50 ps one sigma  
Stored in the chip’s ROM is the ability to generate nine  
different multiplication factors, allowing one chip to  
output many common frequencies (see table on page  
2).  
This product is intended for clock generation. It has low  
output jitter (variation in the output period), but input to  
output skew and jitter are not defined or guaranteed.  
For applications which require defined input to output  
skew, use the ICS570B.  
Duty cycle of 45/55 up to 160 MHz  
Operating voltages of 3.0 to 5.5V  
25 mA drive capability at TTL levels  
Advanced, low power CMOS process  
Block Diagram  
VDD  
CLK  
2
S1, S0  
PLL Clock  
Multiplier  
Circuitry and  
ROM  
X1/ICLK  
Crystal or  
Crystal  
Clock input  
OScillator  
X2  
Optional crystal  
capacitors  
GND  
IDT™ / ICS™ LOCO™ PLL CLOCK MULTIPLIER  
1
ICS503  
REV D 051310  

ICS503MT 替代型号

型号 品牌 替代类型 描述 数据表
ICS502MLF IDT

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