Datasheet > ICS507-01-DWFLF

ICS507-01-DWFLF

更新时间： 2024-11-01 08:54:15

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
5页	62K
描述
Clock Generator, 200MHz, CMOS, DIE

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ICS507-01-DWFLF 数据手册

ICS507-01

PECL Clock Synthesizer

Description

Features

• Packaged as 16 pin narrow SOIC

• Input crystal frequency of 5 - 27 MHz

• Input clock frequency of 5 - 52 MHz

• Enable usage of common low-cost crystal

• Differential PECL output clock frequencies up

to 200 MHz

The ICS507-01 is an inexpensive, simple way

to generate a low jitter 155.52 MHz (or other high

speed) differential PECL clock output from a low

frequency crystal input. Using Phase-Locked-Loop

(PLL) techniques, the devices use a standard

fundamental mode crystal to produce output clocks up

to 200 MHz.

• Duty cycle of 49/51

Stored in each chip’s ROM is the ability to generate a

selection of different multiples of the input reference

frequency, including an exact 155.52 MHz clock from

common crystals. For lowest jitter and phase noise on

a 155.52 MHz clock, a 19.44 MHz crystal and the x8

selection can be used.

• Operation voltage of 3.3 V or 5.0 V (±5%)

• Ideal for SONET applications and oscillator

manufacturers

• Available in die form

• Industrial temperature versions available

• ICS507-02 is no longer available

This product is intended for clock generation. It has low

output jitter (variation in the output period), but input to

output skew and jitter are not defined nor guaranteed.

Block Diagram

1.1kW

GND

VDD

RES

270

Output

Buffer

PECL

S0:1

Clock Synthesis

and

Control Circuitry

62W

VDD

Crystal

clock

Clock

Buffer/

Crystal

62W

Output

Buffer

PECL

Oscillator

270W

Output Enable

(both outputs)

Output resistor values shown are for unterminated lines. Refer to MAN09 for additional information.

MDS 507 H

Revision 092503

Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA •95126• (408)295-9800tel • www.icst.com

12 3 4 5

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