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ICS507M-01ILF PDF预览

ICS507M-01ILF

更新时间: 2024-11-01 14:51:19
品牌 Logo 应用领域
艾迪悌 - IDT 时钟光电二极管外围集成电路晶体
页数 文件大小 规格书
7页 127K
描述
Clock Generator, 125MHz, PDSO16, 0.150 INCH, LEAD FREE, SOIC-16

ICS507M-01ILF 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:0.150 INCH, LEAD FREE, SOIC-16针数:16
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.76
其他特性:ALSO OPERATES AT 5V SUPPLYJESD-30 代码:R-PDSO-G16
JESD-609代码:e3长度:9.9 mm
湿度敏感等级:3端子数量:16
最高工作温度:85 °C最低工作温度:-40 °C
最大输出时钟频率:125 MHz封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP16,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):260电源:3.3/5 V
主时钟/晶体标称频率:52 MHz认证状态:Not Qualified
座面最大高度:1.75 mm子类别:Clock Generators
最大压摆率:63 mA最大供电电压:3.465 V
最小供电电压:3.135 V标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn) - annealed
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:3.9 mmuPs/uCs/外围集成电路类型:CLOCK GENERATOR, OTHER
Base Number Matches:1

ICS507M-01ILF 数据手册

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DATASHEET  
PECL CLOCK SYNTHESIZER  
ICS507-01  
Description  
Features  
The ICS507-01 is an inexpensive, simple way to  
generate a low jitter 155.52 MHz (or other high speed)  
differential PECL clock output from a low frequency  
crystal input. Using Phase-Locked-Loop (PLL)  
techniques, the devices use a standard fundamental  
mode crystal to produce output clocks up to 200 MHz.  
Packaged in 16 pin SOIC  
Available in Pb (lead) free package  
Input crystal frequency of 5 - 27 MHz  
Input clock frequency of 5 - 52 MHz  
Enable usage of common low-cost crystal  
Stored in each chip’s ROM is the ability to generate a  
selection of different multiples of the input reference  
frequency, including an exact 155.52 MHz clock from  
common crystals. For lowest jitter and phase noise on  
a 155.52 MHz clock, a 19.44 MHz crystal and the x8  
selection can be used.  
Differential PECL output clock frequencies up to 200  
MHz  
Duty cycle of 49/51  
Operation voltage of 3.3 V or 5.0 V (±5%)  
Ideal for SONET applications and oscillator  
manufacturers  
This product is intended for clock generation. It has low  
output jitter (variation in the output period), but input to  
output skew and jitter are not defined nor guaranteed.  
Available in die form  
Industrial temperature versions available  
ICS507-02 is no longer available  
Block Diagram  
VDD  
1.1 kohm  
RES  
270 ohm  
2
PECL  
S0:1  
62 ohm  
Clock  
Synthesis  
and Control  
Circuitry  
VDD  
X1/ICLK  
Clock  
Crystal or  
62 ohm  
Buffer/  
Crystal  
clock input  
PECL  
Oscillator  
X2  
270 ohm  
Output Enable  
(both outputs)  
GND  
Output resistors shown are for unterminated lines. Refer to MAN09 for additional information.  
IDT™ / ICS™ PECL CLOCK SYNTHESIZER  
1
ICS507-01  
REV I 041905  

ICS507M-01ILF 替代型号

型号 品牌 替代类型 描述 数据表
ICS507M-01I IDT

完全替代

Clock Generator, 125MHz, CMOS, PDSO16, 0.150 INCH, SOIC-16

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