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ICS511MILF

更新时间: 2024-11-05 20:30:23
品牌 Logo 应用领域
艾迪悌 - IDT 时钟光电二极管外围集成电路晶体
页数 文件大小 规格书
8页 87K
描述
Clock Generator, 160MHz, CMOS, PDSO8, 0.150 INCH, LEAD FREE, SOIC-8

ICS511MILF 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:SOIC
包装说明:SOP, SOP8,.25针数:8
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.17
Is Samacsys:N其他特性:ALSO OPERATES AT 3.3V AT 145 MHZ
JESD-30 代码:R-PDSO-G8JESD-609代码:e3
长度:4.9 mm湿度敏感等级:1
端子数量:8最高工作温度:85 °C
最低工作温度:-40 °C最大输出时钟频率:160 MHz
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP8,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):260
电源:3.3/5 V主时钟/晶体标称频率:50 MHz
认证状态:Not Qualified座面最大高度:1.75 mm
子类别:Clock Generators最大供电电压:5.25 V
最小供电电压:4.75 V标称供电电压:5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn) - annealed
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:3.9 mmuPs/uCs/外围集成电路类型:CLOCK GENERATOR, OTHER
Base Number Matches:1

ICS511MILF 数据手册

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ICS511  
LOCOTM PLL CLOCK MULTIPLIER  
Description  
Features  
TM  
The ICS511 LOCO is the most cost effective way to  
generate a high quality, high frequency clock output  
from a lower frequency crystal or clock input. The name  
LOCO stands for Low Cost Oscillator, as it is designed  
to replace crystal oscillators in most electronic  
systems. Using Phase-Locked Loop (PLL) techniques,  
the device uses a standard fundamental mode,  
inexpensive crystal to produce output clocks up to 200  
MHz.  
Packaged as 8-pin SOIC or die  
Available in Pb (lead) free package  
Upgrade of popular ICS501 with:  
- changed multiplier table  
- faster operating frequencies  
- output duty cycle at VDD/2  
Zero ppm multiplication error  
Input crystal frequency of 5 - 27 MHz  
Input clock frequency of 2 - 50 MHz  
Output clock frequencies up to 200 MHz  
Extremely low jitter of 25 ps (one sigma)  
Compatible with all popular CPUs  
Duty cycle of 45/55 up to 200 MHz  
Mask option for nine selectable frequencies  
Operating voltage of 3.3 V or 5 V  
Tri-state output for board level testing  
Industrial temperature version available  
Advanced, low power CMOS process  
Stored in the chip’s ROM is the ability to generate nine  
different multiplication factors, allowing one chip to  
output many common frequencies (see table on page  
2).  
The device also has an output enable pin which  
tri-states the clock output when the OE pin is taken low.  
This product is intended for clock generation. It has low  
output jitter (variation in the output period), but input to  
output skew and jitter are not defined nor guaranteed.  
For applications which require defined input to output  
skew, use the ICS570B.  
Block Diagram  
VDD  
2
S1:0  
PLL Clock  
Multiplier  
Circuitry  
and ROM  
X1/ICLK  
CLK  
Crystal or  
Clock input  
Crystal  
Oscillator  
X2  
Optional crystal capacitors  
OE  
GND  
MDS 511 G  
1
Revision 102504  
Integrated Circuit Systems 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com  

ICS511MILF 替代型号

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