ICS507-01/02
PECL Clock Synthesizer
Description
Features
The ICS507-01 and ICS507-02 are inexpensive
ways to generate a low jitter 155.52 MHz (or other
high speed) differential PECL clock output from a
low frequency crystal input. Using Phase-Locked-
Loop (PLL) techniques, the devices use a standard
fundamental mode crystal to produce output
clocks up to 200 MHz.
• Packaged as 16 pin narrow SOIC or die
• Input crystal frequency of 5 - 27 MHz
• Input clock frequency of 5 - 52 MHz
• Uses low-cost crystal
• Differential PECL output clock frequencies up
to 200 MHz
Stored in each chip’s ROM is the ability to
generate a selection of different multiples of the
input reference frequency, including an exact
155.52 MHz clock from common crystals. For
lowest jitter and phase noise on a 155.52 MHz
clock, a 19.44 MHz crystal and the x8 selection
can be used.
• Duty cycle of 49/51
• 3.3 V or 5.0 V±10% operating supply
• Ideal for SONET applications and oscillator
manufacturers
• Advanced, low power CMOS process
• Industrial temperature versions available
Block Diagram
1.1kΩ
GND
VDD
RES
270Ω
Output
2
PECL
S0:1
Buffer
62Ω
Clock Synthesis
and Control
Circuitry
VDD
Crystal
or
clock
X1
X2
Clock
Buffer/
Crystal
62Ω
Output
Buffer
PECL
Oscillator
270Ω
Output resistor values shown are for unterminated lines.
Refer to MAN09 for additional information.
Output Enable
(both outputs)
MDS 507 C
1
Revision 042600
Printed 11/13/00
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA •95126• (408)295-9800tel • www.icst.com