Datasheet > ICS507M-01DPKLF

ICS507M-01DPKLF

更新时间： 2024-11-02 07:13:11

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
7页	135K
描述
Clock Generator, 200MHz, DIE

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ICS507M-01DPKLF 数据手册

ICS507-01

PECL CLOCK SYNTHESIZER

Description

Features

The ICS507-01 is an inexpensive, simple way to

generate a low jitter 155.52 MHz (or other high speed)

differential PECL clock output from a low frequency

crystal input. Using Phase-Locked-Loop (PLL)

techniques, the devices use a standard fundamental

mode crystal to produce output clocks up to 200 MHz.

• Packaged in 16 pin SOIC

• Available in Pb (lead) free package

• Input crystal frequency of 5 - 27 MHz

• Input clock frequency of 5 - 52 MHz

• Enable usage of common low-cost crystal

Stored in each chip’s ROM is the ability to generate a

selection of different multiples of the input reference

frequency, including an exact 155.52 MHz clock from

common crystals. For lowest jitter and phase noise on

a 155.52 MHz clock, a 19.44 MHz crystal and the x8

selection can be used.

• Differential PECL output clock frequencies up to 200

MHz

• Duty cycle of 49/51

• Operation voltage of 3.3 V or 5.0 V ( 5ꢀ)

• Ideal for SONET applications and oscillator

manufacturers

This product is intended for clock generation. It has low

output jitter (variation in the output period), but input to

output skew and jitter are not defined nor guaranteed.

• Available in die form

• Industrial temperature versions available

• ICS507-02 is no longer available

Block Diagram

VDD

1.1 kohm

RES

270 ohm

PECL

S0:1

62 ohm

Clock

Synthesis

and Control

Circuitry

VDD

X1/ICLK

Clock

Crystal or

62 ohm

Buffer/

Crystal

clock input

PECL

Oscillator

270 ohm

Output Enable

(both outputs)

GND

Output resistors shown are for unterminated lines. Refer to MAN09 for additional information.

MDS 507-01 I

Revision 041905

Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com

12 3 4 5 6 7

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