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HY5R256HC PDF预览

HY5R256HC

更新时间: 2024-09-16 23:57:15
品牌 Logo 应用领域
其他 - ETC 动态存储器
页数 文件大小 规格书
64页 4001K
描述
-|2.5V|8K|40|Direct RDRAM - 256M

HY5R256HC 数据手册

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Direct RDRAM™  
256/288-Mbit (512Kx16/18x32s) Preliminary  
Overview  
The Rambus Direct RDRAM™ is a general purpose high-  
performance memory device suitable for use in a broad  
range of applications including computer memory, graphics,  
video, and any other application where high bandwidth and  
low latency are required.  
The 256/288-Mbit Direct Rambus DRAMs (RDRAM)are  
extremely high-speed CMOS DRAMs organized as 16M  
words by 16 or 18 bits. The use of Rambus Signaling Level  
(RSL) technology permits 600MHz to 800MHz transfer  
rates while using conventional system and board design  
technologies. Direct RDRAM devices are capable of  
sustained data transfers at 1.25 ns per two bytes (10ns per  
sixteen bytes).  
The architecture of the Direct RDRAMs allows the highest  
sustained bandwidth for multiple, simultaneous randomly  
addressed memory transactions. The separate control and  
data buses with independent row and column control yield  
over 95% bus efficiency. The Direct RDRAM's 32 banks  
support up to four simultaneous transactions.  
Figure 1: Direct RDRAM uBGA Package  
The 256/288-Mbit Direct RDRAMs are offered in a uBGA  
package suitable for desktop as well as low-profile add-in  
card and mobile applications.  
System oriented features for mobile, graphics and large  
memory systems include power management, byte masking,  
and x18 organization. The two data bits in the x18 organiza-  
tion are general and can be used for additional storage and  
bandwidth or for error correction.  
Direct RDRAMs operate from a 2.5 volt supply.  
Key Timing Parameters / Part Numbers  
Features  
I/O Freq. Core Access Time  
Part  
Number  
Organizationa  
MHz  
(ns)  
0 Highest sustained bandwidth per DRAM device  
- 1.6GB/s sustained data transfer rate  
- Separate control and data buses for maximized  
efficiency  
- Separate row and column control buses for  
easy scheduling and highest performance  
- 32 banks: four transactions can take place simul-  
taneously at full bandwidth data rates  
512Kx16x32s  
512Kx16x32s  
512Kx16x32s  
512Kx16x32s  
512Kx18x32s  
512Kx18x32s  
512Kx18x32s  
512Kx18x32s  
600  
711  
800  
800  
600  
711  
800  
800  
53  
45  
45  
40  
53  
45  
45  
40  
HY5R256HC653  
HY5R256HC745  
HY5R256HC845  
HY5R256HC840  
HY5R288HC653  
HY5R288HC745  
HY5R288HC845  
HY5R288HC840  
0 Low latency features  
- Write buffer to reduce read latency  
- 3 precharge mechanisms for controller flexibility  
- Interleaved transactions  
a. The bank 32s” designation indicates that this RDRAM core is  
composed of 32 banks which use a split” bank architecture.  
0 Advanced power management:  
- Multiple low power states allows flexibility in power  
consumption versus time to transition to active state  
- Power-down self-refresh  
0 Organization: 2Kbyte pages and 32 banks, x 16/18  
- x18 organization allows ECC configurations or  
increased storage/bandwidth  
- x16 organization for low cost applications  
0 Uses Rambus Signaling Level (RSL) for up to 800MHz  
operation  
Rev. 0.9 / Dec.2000  
1
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of  
circuits described. No patent licenses are implied.  

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