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HSP45240JC-33 PDF预览

HSP45240JC-33

更新时间： 2024-01-23 03:50:30
品牌 Logo 应用领域
英特矽尔 - INTERSIL 外围集成电路双倍数据速率时钟
页数 文件大小 规格书
13页 283K
描述
Address Sequencer

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中文翻译

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HSP45240JC-33 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Contact Manufacturer零件包装代码：QFN
包装说明：,针数：68
Reach Compliance Code：unknownECCN代码：3A991.A.2
HTS代码：8542.39.00.01风险等级：5.71
Is Samacsys：N其他特性：24 X 24 CROSSPOINT SWITCH
边界扫描：NO最大时钟频率：33 MHz
外部数据总线宽度：7JESD-30 代码：S-PQCC-J68
JESD-609代码：e0低功率模式：NO
湿度敏感等级：4端子数量：68
最高工作温度：70 °C最低工作温度：
输出数据总线宽度：24封装主体材料：PLASTIC/EPOXY
封装形状：SQUARE封装形式：CHIP CARRIER
峰值回流温度（摄氏度）：225认证状态：Not Qualified
最大供电电压：5.25 V最小供电电压：4.75 V
标称供电电压：5 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：TIN LEAD端子形式：J BEND
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
uPs/uCs/外围集成电路类型：DSP PERIPHERAL, ADDRESS SEQUENCERBase Number Matches：1

HSP45240JC-33 数据手册

 浏览型号HSP45240JC-33的Datasheet PDF文件第2页浏览型号HSP45240JC-33的Datasheet PDF文件第3页浏览型号HSP45240JC-33的Datasheet PDF文件第4页浏览型号HSP45240JC-33的Datasheet PDF文件第5页浏览型号HSP45240JC-33的Datasheet PDF文件第6页浏览型号HSP45240JC-33的Datasheet PDF文件第7页 
®
HSP45240  
Address Sequencer  
July 2004  
Features  
Des cription  
• Block Oriented 24-Bit Sequencer  
• Configurable as Two Independent 12-Bit Sequencers  
• 24 x 24 Crosspoint Switch  
The Intersil HSP45240 is a high speed Address Sequencer  
which provides specialized addressing for functions like  
FFTs, 1-D and 2-D filtering, matrix operations, and image  
manipulation. The sequencer supports block oriented  
addressing of large data sets up to 24-bits at clock speeds  
up to 50MHz.  
• Programmable Delay on 12 Outputs  
• Multi-Chip Synchronization Signals  
• Standard µP Interface  
Specialized addressing requirements are met by using the  
onboard 24 x 24 crosspoint switch. This feature allows the map-  
ping of the 24 address bits at the output of the address genera-  
tor to the 24 address outputs of the chip. As a result, bit reverse  
addressing, such as that used in FFTs, is made possible.  
• 100pF Drive on Outputs  
• DC to 50MHz Clock Rate  
A single chip solution to read/write addressing is also made  
possible by configuring the HSP45240 as two 12-bit  
sequencers. To compensate for system pipeline delay, a  
programmable delay is provided on 12 of the address out-  
puts.  
Applications  
• 1-D, 2-D Filtering  
• Pan/Zoom Addressing  
• FFT Processing  
The HSP45240 is manufactured using an advanced CMOS  
process, and is a low power fully static design. The configu-  
ration of the device is controlled through a standard micro-  
processor interface and all inputs/outputs, with the exception  
of clock, are TTL compatible.  
• Matrix Math Operations  
Ordering Information  
TEMP.  
PKG.  
DWG. #  
PART NUMBER  
HSP45240JC-33  
HSP45240JC-50  
RANGE (°C)  
PACKAGE  
68 Ld PLCC  
68 Ld PLCC  
0 to 70  
0 to 70  
N68.95  
N68.95  
Block Diagram  
STARTOUT  
ADDVAL  
DONE  
BLOCKDONE  
12  
OUT12-23  
REG  
STARTIN  
24  
CROSSPOINT  
SWITCH  
START  
CIRCUITRY  
SEQUENCE  
GENERATOR  
OEH  
12  
DELAY  
1-8  
OUT0-11  
DLYBLK  
OEL  
BUSY  
PROCESSOR INTERFACE  
D0-6, CS, A0, WR  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc.  
FN2489.4  
Copyright Harris Corporation 1997, Copyright Intersil Americas Inc. 2004. All Rights Reserved  
1
All other trademarks mentioned are the property of their respective owners.  
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