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HSP45256GC-33 PDF预览

HSP45256GC-33

更新时间： 2024-11-15 20:15:43
品牌 Logo 应用领域
瑞萨 - RENESAS 时钟外围集成电路
页数 文件大小 规格书
23页 290K
描述
8-BIT, DSP-CORRELATOR, CPGA85, PGA-85

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HSP45256GC-33 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：PGA包装说明：PGA-85
针数：85Reach Compliance Code：not_compliant
ECCN代码：3A991.A.2HTS代码：8542.39.00.01
风险等级：5.72Is Samacsys：N
其他特性：ICC SPECIFIED AT 25.6MHZ边界扫描：NO
最大时钟频率：33 MHz外部数据总线宽度：8
JESD-30 代码：S-CPGA-P85JESD-609代码：e0
长度：29.465 mm低功率模式：YES
端子数量：85最高工作温度：70 °C
最低工作温度：输出数据总线宽度：8
封装主体材料：CERAMIC, METAL-SEALED COFIRED封装代码：PGA
封装等效代码：PGA84M,11X11封装形状：SQUARE
封装形式：GRID ARRAY峰值回流温度（摄氏度）：NOT SPECIFIED
电源：5 V认证状态：Not Qualified
座面最大高度：5.2 mm子类别：DSP Peripherals
最大压摆率：232 mA最大供电电压：5.25 V
最小供电电压：4.75 V标称供电电压：5 V
表面贴装：NO技术：CMOS
温度等级：COMMERCIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：PIN/PEG端子节距：2.54 mm
端子位置：PERPENDICULAR处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：29.465 mmuPs/uCs/外围集成电路类型：DSP PERIPHERAL, CORRELATOR
Base Number Matches：1

HSP45256GC-33 数据手册

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HSP45256  
TM  
Data Sheet  
May 1999  
FN2814.4  
Binary Correlator  
Features  
The Intersil HSP45256 is a high-speed, 256 tap binary  
correlator. It can be configured to perform one-dimensional  
or two-dimensional correlations of selectable data precision  
and length. Multiple HSP45256’s can be cascaded for  
increased correlation length. Unused taps can be masked  
out for reduced correlation length.  
• Reconfigurable 256 Stage Binary Correlator  
• 1-Bit Reference x 1, 2, 4, or 8-Bit Data  
• Separate Control and Reference Interfaces  
• 25.6, 33MHz Versions  
• Configurable for 1-D and 2-D Operation  
• Double Buffered Mask and Reference  
• Programmable Output Delay  
The correlation array consists of eight 32-tap stages. These  
may be cascaded internally to compare 1, 2, 4 or 8-bit input  
data with a 1-bit reference. Depending on the number of bits  
in the input data, the length of the correlation can be up to  
256, 128, 64, or 32 taps. The HSP45256 can also be  
configured as two separate correlators with window sizes  
from 4 by 32 to 1 by 128 each. The mask register can be  
used to prevent any subset of the 256 bits from contributing  
to the correlation score.  
• Cascadable  
• Standard Microprocessor Interface  
Applications  
• Radar/Sonar  
The output of the correlation array (correlation score) feeds  
the weight and sum logic, which gives added flexibility to the  
data format. In addition, an offset register is provided so that  
a preprogrammed value can be added to the correlation  
score. This result is then passed through a user  
• Spread Spectrum Communications  
• Pattern/Character Recognition  
- Error Correction Coding  
Ordering Information  
programmable delay stage to the cascade summer. The  
delay stage simplifies the cascading of multiple correlators  
by compensating for the latency of previous correlators.  
TEMP.  
o
PKG.  
NO.  
PART NUMBER RANGE ( C)  
PACKAGE  
84 Ld PLCC  
HSP45256JC-25  
HSP45256JC-33  
HSP45256GC-25  
HSP45256GC-33  
HSP45256JI-25  
HSP45256JI-33  
0 to 70  
0 to 70  
N84.1.15  
N84.1.15  
G85.A  
The Binary Correlator is configured by writing a set of control  
registers via a standard microprocessor interface. To simplify  
operation, both the control and reference registers are  
double buffered. This allows the user to load new mask and  
reference data while the current correlation is in progress.  
84 Ld PLCC  
85 Ld PGA  
85 Ld PGA  
84 Ld PLCC  
84 Ld PLCC  
0 to 70  
0 to 70  
G85.A  
-40 to 85  
-40 to 85  
N84.1.15  
N84.1.15  
Block Diagram  
DOUT  
DOUT0-7  
DIN0-7  
256 TAP  
CORRELATION  
ARRAY  
DREFOUT  
CSCORE  
AUXOUT0-8  
MUX  
DREF0-7  
WEIGHT  
AND SUM  
DCONT0-7  
A0-2  
CONTROL  
CASCADE  
SUMMER  
CASOUT0-12  
DELAY  
CASIN0-12  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc.  
Copyright © Intersil Americas Inc. 2002. All Rights Reserved  
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