Datasheet > HSP48212JC-40

HSP48212JC-40

更新时间： 2024-01-12 07:07:29

品牌	Logo	应用领域
英特矽尔 - INTERSIL		/
页数	文件大小	规格书
9页	61K
描述
Digital Video Mixer

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技术参数
数据手册

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HSP48212JC-40 技术参数

是否Rohs认证：	不符合	生命周期：	Transferred
包装说明：	,	Reach Compliance Code：	unknown
ECCN代码：	3A991.A.2	HTS代码：	8542.39.00.01
风险等级：	8.76	其他特性：	PROGRAMMABLE PIPELINE DELAY OF UP TO 7 CLOCK CYCLES
边界扫描：	NO	最大时钟频率：	40 MHz
外部数据总线宽度：	12	JESD-30 代码：	S-PQCC-J68
JESD-609代码：	e0	低功率模式：	NO
端子数量：	68	最高工作温度：	70 °C
最低工作温度：		输出数据总线宽度：	13
封装主体材料：	PLASTIC/EPOXY	封装形状：	SQUARE
封装形式：	CHIP CARRIER	认证状态：	Not Qualified
最大压摆率：	170 mA	最大供电电压：	5.25 V
最小供电电压：	4.75 V	标称供电电压：	5 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	J BEND	端子位置：	QUAD
uPs/uCs/外围集成电路类型：	DSP PERIPHERAL, MIXER

HSP48212JC-40 数据手册

HSP48212

Data Sheet

May 1999

File Number 3627.2

Digital Video Mixer

Features

The Intersil HSP48212 is a 68 pin Digital Video Mixer IC

intended for use in multimedia and medical imaging

applications.

• 12-Bit Pixel Data

• Two’s Complement or Unsigned Data

• 12-Bit Mix Factor

The HSP48212 allows the user to mix two video sources

based on a programmable weighting factor. After weighting

the input data signals, the Video Mixer simply adds the two

weighted signals mathematically. This results in the mixed

output, which is a weighted sum of the two sources.

• 13-Bit Signed or Unsigned Three State Output

• Overﬂow Detection and Output Saturation

• Rounding to 8, 10, 12, or 13-Bits

• Input and Output Pixel Data Synchronous to Clock

The input and output interfaces are synchronous with respect

to the input clock, simplifying the user interface requirements.

• Programmable Pipeline Delay of up to 7 Clock Cycles for

Control of Misaligned Input Data

Input Data (DINA, DINB), Mix Factor (M) and control signals

(RND, TCB) may be delayed relative to each other in order to

compensate for any misalignment that may have occurred

prior to entering the HSP48212. Each input’s delay may be

independently programmed up to seven clock cycles.

• TTL Compatible Inputs/Outputs

• DC to 40MHz Clock Rate

Applications

The output data may be rounded to 8, 10, 12, or 13-bits. The

enabling of data onto the output data bus is under the user’s

control via an output enable signal (OE).

• Video Summing (Frame Addition)

• Video Mixing

• Fade In/Out

Ordering Information

• Video Switching

TEMP.

• High Speed Multiplying

PART NUMBER RANGE ( C)

PACKAGE

64 Ld MQFP

68 Ld PLCC

PKG. NO.

Q64.14x14

N68.95

HSP48212VC-40

HSP48212JC-40

0 to 70

Block Diagram

DELAY

0-7

TCB

DELAY

0-7

DELAY

0-7

RND0-1

DINB0-11

1-M

SHIFT

LEFT

DELAY

0-7

DOUT0-12

DELAY

0-7

DINA0-11

DOUT = 2 x [DINA x M + DINB x (1-M)]

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

12 3 4 5 6 7...9

中文翻译

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与HSP48212JC-40相关器件

型号	品牌	获取价格	描述	数据表
HSP48212VC-40	INTERSIL	获取价格	Digital Video Mixer
HSP48410	INTERSIL	获取价格	Histogrammer/Accumulating Buffer
HSP48410/883	INTERSIL	获取价格	Histogrammer/Accumulating Buffer
HSP48410_04	INTERSIL	获取价格	Histogrammer/Accumulating Buffer
HSP48410883	INTERSIL	获取价格	Histogrammer/Accumulating Buffer
HSP48410GC-33	INTERSIL	获取价格	Histogrammer/Accumulating Buffer
HSP48410GC-40	INTERSIL	获取价格	Histogrammer/Accumulating Buffer
HSP48410GC-40	RENESAS	获取价格	24-BIT, DSP-HISTOGRAM PROCESSOR, CPGA84, PGA-84
HSP48410GM-25/883	INTERSIL	获取价格	Histogrammer/Accumulating Buffer
HSP48410GM-33/883	INTERSIL	获取价格	Histogrammer/Accumulating Buffer

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