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HSP48901GC-20 PDF预览

HSP48901GC-20

更新时间： 2024-02-21 13:47:03
品牌 Logo 应用领域
英特矽尔 - INTERSIL 过滤器外围集成电路输入元件LTE时钟
页数 文件大小 规格书
9页 66K
描述
3 x 3 Image Filter

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中文翻译

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HSP48901GC-20 技术参数

生命周期：Active零件包装代码：PGA
包装说明：,针数：68
Reach Compliance Code：unknown风险等级：5.66
Is Samacsys：N其他特性：3 X 8 BIT DATA INPUT BUS
边界扫描：NO最大时钟频率：20 MHz
外部数据总线宽度：8JESD-30 代码：S-CPGA-P68
低功率模式：NO端子数量：68
最高工作温度：70 °C最低工作温度：
输出数据总线宽度：20封装主体材料：CERAMIC, METAL-SEALED COFIRED
封装形状：SQUARE封装形式：GRID ARRAY
认证状态：COMMERCIAL最大供电电压：5.25 V
最小供电电压：4.75 V标称供电电压：5 V
表面贴装：NO技术：CMOS
温度等级：COMMERCIAL端子形式：PIN/PEG
端子位置：PERPENDICULARuPs/uCs/外围集成电路类型：DSP PERIPHERAL, DIGITAL FILTER
Base Number Matches：1

HSP48901GC-20 数据手册

 浏览型号HSP48901GC-20的Datasheet PDF文件第2页浏览型号HSP48901GC-20的Datasheet PDF文件第3页浏览型号HSP48901GC-20的Datasheet PDF文件第4页浏览型号HSP48901GC-20的Datasheet PDF文件第5页浏览型号HSP48901GC-20的Datasheet PDF文件第6页浏览型号HSP48901GC-20的Datasheet PDF文件第7页 
HSP48901  
Data Sheet  
May 1999  
File Number 2459.5  
3 x 3 Image Filter  
Features  
The Intersil HSP48901 is a high speed 9-Tap FIR Filter  
which utilizes 8-bit wide data and coefficients. It can be  
configured as a one dimensional (1-D) 9-Tap filter for a  
variety of signal processing applications, or as a two  
dimensional (2-D) filter for image processing. In the 2-D  
configuration, the device is ideally suited for implementing 3  
x 3 kernel convolution. The 30MHz clock rate allows a large  
number of image sizes to be processed within the required  
frame time for real-time video.  
• DC to 30MHz Clock Rate  
• Configurable for 1-D and 2-D Correlation/Convolution  
• Dual Coefficient Mask Registers, Switchable in a Single  
Clock Cycle  
• Two’s Complement or Unsigned 8-Bit Input Data and  
Coefficients  
• 20-Bit Extended Precision Output  
• Standard µP Interface  
Data is provided to the HSP48901 through the use of  
programmable data buffers such as the HSP9500 or any  
other Programmable Shift Register. Coefficient and pixel  
input data are 8-bit signed or unsigned integers, and the  
20-bit extended output guarantees no overflow will occur  
during the filtering operation.  
Applications  
• Image Filtering  
• Edge Detection/Enhancement  
• Pattern Matching  
• Real Time Video Filters  
There are two internal register banks for storing independent  
3 x 3 filter kernels, thus, facilitating the implementation of  
adaptive filters and multiple filter operations on the same  
data.  
Ordering Information  
TEMP.  
PKG.  
NO.  
o
PART NUMBER RANGE ( C)  
PACKAGE  
68 Ld PLCC  
The configuration of the HSP48901 Image Filter is controlled  
through a standard microprocessor interface and all inputs  
and outputs are TTL compatible.  
HSP48901JC-20  
HSP48901JC-30  
HSP48901GC-20  
HSP48901GC-30  
0 to 70  
0 to 70  
0 to 70  
0 to 70  
N68.95  
N68.95  
G68.A  
G68.A  
68 Ld PLCC  
68 Ld PGA  
68 Ld PGA  
Block Diagram  
-1  
DIN3 (0-7)  
DIN2 (0-7)  
DIN1 (0-7)  
Z
Z
Z
-1  
-1  
2:1  
2:1  
MODE  
MODE  
-1  
-1  
-1  
-1  
-1  
-1  
-1  
Z
CIN0-7  
Z
Z
Z
Z
Z
Z
CONTROL  
LOGIC  
FRAME  
-1  
Z
3
ADDRESS  
DECODER  
A0-2  
LD  
-1  
Z
I
H
G
F
E
Z
Z
D
C
B
A
INTERNAL  
CLOCK  
CLK  
CLOCK  
GEN  
-1  
-1  
-1  
-1  
-1  
-1  
-1  
-1  
-1  
Z
Z
Z
Z
Z
Z
Z
Z
HOLD  
+
+
+
-1  
+
-1  
Z
DOUT 0-19  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999  
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