Datasheet > HSP50016JC-75

HSP50016JC-75

更新时间： 2024-11-14 22:20:39

品牌	Logo	应用领域
英特矽尔 - INTERSIL		外围集成电路时钟
页数	文件大小	规格书
31页	211K
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Digital Down Converter

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HSP50016JC-75 数据手册

HSP50016

Data Sheet

February 1999

File Number 3288.6

Digital Down Converter

Features

The Digital Down Converter (DDC) is a single chip

synthesizer, quadrature mixer and lowpass ﬁlter. Its input

data is a sampled data stream of up to 16 bits in width and

up to a 75 MSPS data rate. The DDC performs down

conversion, narrowband low pass ﬁltering and decimation to

produce a baseband signal.

• 75 MSPS Input Data Rate

• 16-Bit Data Input; Offset Binary or 2’s Complement

Format

• Spurious Free Dynamic Range Through Modulator

>102dB

• Frequency Selectivity: <0.006Hz

• Identical Lowpass Filters for I and Q

• Passband Ripple: <0.04dB

The internal synthesizer can produce a variety of signal

formats. They are: CW, frequency hopped, linear FM up

chirp, and linear FM down chirp. The complex result of the

modulation process is lowpass ﬁltered and decimated with

identical real ﬁlters in the in-phase (I) and quadrature (Q)

processing chains.

• Stopband Attenuation: >104dB

• Filter -3dB to -102dB Shape Factor: <1.5

• Decimation Factors from 32 to 131,072

• IEEE 1149.1 Test Access Port

Lowpass ﬁltering is accomplished via a High Decimation

Filter (HDF) followed by a ﬁxed Finite Impulse Response

(FIR) ﬁlter. The combined response of the two stage ﬁlter

results in a -3dB to -102dB shape factor of better than 1.5.

The stopband attenuation is greater than 106dB. The

composite passband ripple is less than 0.04dB. The

synthesizer and mixer can be bypassed so that the chip

operates as a single narrow band low pass ﬁlter.

• HSP50016-EV Evaluation Board Available

Applications

• Cellular Base Stations

• Smart Antennas

• Channelized Receivers

• Spectrum Analysis

The chip receives forty bit serial commands as a control

input. This interface is compatible with the serial I/O port

available on most microprocessors.

• Related Products: HI5703, HI5746, HI5766 A/Ds

The output data can be conﬁgured in ﬁxed point or single

precision ﬂoating point. The ﬁxed point formats are 16,

24, 32, or 38-bit, two’s complement, signed magnitude, or

offset binary.

Ordering Information

PART

NUMBER

TEMP. RANGE

PKG.

NO.

( C)

PACKAGE

44 Ld PLCC

48 Ld CPGA

HSP50016JC-52

HSP50016JC-75

HSP50016GC-52

0 to 70

N44.65

G48.A

The circuit provides an IEEE 1149.1 Test Access Port.

Block Diagram

HIGH DECIMATION

LOW PASS FIR

FILTER

DATA

CLK

FILTER

OUTPUT

HIGH DECIMATION

FILTER

LOW PASS FIR

FILTER

COS

CONTROL

SIN

IQSTRB

COMPLEX

SINUSOID

GENERATOR

CLK

IQCLK

CLK

TEST ACCESS

PORT

TEST ACCESS

PORT/CTRL

CLK

SER

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

3-198

12 3 4 5 6 7...31

中文翻译

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