Datasheet > HSP50214BVC

HSP50214BVC

更新时间： 2024-11-14 22:33:59

品牌	Logo	应用领域
英特矽尔 - INTERSIL		电信集成电路
页数	文件大小	规格书
60页	572K
描述
Programmable Downconverter

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HSP50214BVC 数据手册

HSP50214B

Data Sheet

May 2000

File Number 4450.3

Programmable Downconverter

Features

The HSP50214B Programmable Downconverter converts

digitized IF data into ﬁltered baseband data which can be

processed by a standard DSP microprocessor. The

Programmable Downconverter (PDC) performs down

conversion, decimation, narrowband low pass ﬁltering, gain

scaling, resampling, and Cartesian to Polar coordinate

conversion.

• Up to 65 MSPS Front-End Processing Rates (CLKIN) and

55MHz Back-End Processing Rates (PROCCLK)

Clocks May Be Asynchronous

[ /Title

(HSP5

0214B)

/Sub-

ject

• Processing Capable of >100dB SFDR

• Up to 255-Tap Programmable FIR

• Overall Decimation Factor Ranging from 4 to 16384

• Output Samples Rates to 12.94 MSPS with Output

Bandwidths to 982kHz Lowpass

(Pro-

The 14-bit sampled IF input is down converted to baseband

by digital mixers and a quadrature NCO, as shown in the

Block Diagram. A decimating (4 to 32) ﬁfth order Cascaded

Integrator-Comb (CIC) ﬁlter can be applied to the data

before it is processed by up to 5 decimate-by-2 halfband

ﬁlters. The halfband ﬁlters are followed by a 255-tap

programmable FIR ﬁlter. The output data from the

programmable FIR ﬁlter is scaled by a digital AGC before

being re-sampled in a polyphase FIR ﬁlter. The output

section can provide seven types of data: Cartesian (I, Q),

polar (R, θ), ﬁltered frequency (dθ/dt), Timing Error (TE), and

AGC level in either parallel or serial format.

gram-

mable

Down-

con-

verter)

/Autho

r ()

/Key-

words

(Inter-

sil

Corpo-

ration,

Down-

con-

• 32-Bit Programmable NCO for Channel Selection and

Carrier Tracking

• Digital Resampling Filter for Symbol Tracking Loops and

Incommensurate Sample-to-Output Clock Ratios

• Digital AGC with Programmable Limits and Slew Rate to

Optimize Output Signal Resolution; Fixed or Auto Gain

Adjust

• Serial, Parallel, and FIFO 16-Bit Output Modes

• Cartesian to Polar Converter and Frequency Discriminator

for AFC Loops and Demodulation of AM, FM, FSK, and

DPSK

• Input Level Detector for External I.F. AGC Support

Ordering Information

PART

NUMBER

TEMP.

RANGE ( C)

Applications

PACKAGE

120 Ld MQFP

PKG. NO.

Q120.28x28

• Single Channel Digital Software Radio Receivers

HSP50214BVC

HSP50214BVI

0 to 70

• Base Station Rx’s: AMPS, NA TDMA, GSM, and CDMA

verter,

Down

Con-

-40 to 85

• Compatible with HSP50210 Digital Costas Loop for PSK

Reception

• Evaluation Platform Available

verter,

Pro-

gram-

mable

Down-

con-

Block Diagram

MICROPROCESSOR

READ/WRITE

CONTROL

C(7:0)

AGC LOOP FILTER

AGC

LEVEL DETECT

verter,

DSP,

I OUT

POLYPHASE

SEROUTA

ORDER

CIC

FILTER

FIR AND

HALFBAND

FILTERS

CARTESIAN

AMPS,

TDMA

, North

Ameri-

can

MAG.

SEROUTB

AOUT(15:0)

POLAR

IN(13:0)

PHASE

COORDINATE

CONVERTER

ORDER

CIC

FILTER

BOUT(15:0)

POLYPHASE

FIR AND

HALFBAND

FILTERS

GAIN

ADJ

(2:0)

Q OUT

CARRIER

NCO

TDMA

, GSM,

COF

FREQ

SOF

CLKIN

DISCRIMINATOR

RESAMPLING

NCO

TIMING ERROR

PROCCLK

REFCLK

∆

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

3-1

12 3 4 5 6 7...60

中文翻译

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与HSP50214BVC相关器件

型号	品牌	获取价格	描述	数据表
HSP50214BVCZ	INTERSIL	获取价格	Programmable Downconverter
HSP50214BVI	INTERSIL	获取价格	Programmable Downconverter
HSP50214BVIZ	INTERSIL	获取价格	Programmable Downconverter
HSP50214VC	INTERSIL	获取价格	Programmable Downconverter
HSP50214VI	INTERSIL	获取价格	Programmable Downconverter
HSP50215	INTERSIL	获取价格	Digital UpConverter
HSP50215EVAL	INTERSIL	获取价格	DSP Modulator Evaluation Board
HSP50215VC	INTERSIL	获取价格	Digital UpConverter
HSP50215VI	INTERSIL	获取价格	Digital UpConverter
HSP50216	INTERSIL	获取价格	Four-Channel Programmable Digital DownConverter

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