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HSP50306SC-27

更新时间： 2024-01-04 23:28:42
品牌 Logo 应用领域
英特矽尔 - INTERSIL /
页数 文件大小 规格书
8页 41K
描述
Digital QPSK Demodulator

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HSP50306SC-27 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Contact Manufacturer零件包装代码：SOIC
包装说明：SOP,针数：16
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.69Is Samacsys：N
JESD-30 代码：R-PDSO-G16JESD-609代码：e0
长度：10.3 mm功能数量：1
端子数量：16最高工作温度：70 °C
最低工作温度：封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE峰值回流温度（摄氏度）：NOT SPECIFIED
认证状态：Not Qualified座面最大高度：2.65 mm
表面贴装：YES电信集成电路类型：TELECOM CIRCUIT
温度等级：COMMERCIAL端子面层：TIN LEAD
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：7.5 mmBase Number Matches：1

HSP50306SC-27 数据手册

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HSP50306  
Digital QPSK Demodulator  
February 1998  
Features  
Description  
• 25.6MHz or 26.97MHz Clock Rates  
The HSP50306 is a 6-bit QPSK demodulator chip designed  
for use in high signal to noise environments which have some  
multipath distortion. The part recovers 2.048 MBPS data from  
samples of a QPSK modulated 10.7MHz or 2.1MHz carrier.  
The chip coherently demodulates the waveform, recovers  
symbol timing, adaptively equalizes the signal to remove  
multipath distortion, differentially decodes and multiplexes the  
data decisions. 8-A lock signal is provided to indicate when  
the tracking loops are locked and the data decisions are valid.  
To optimize performance, a gain error feedback signal is  
provided which can be filtered and used to close an I.F. AGC  
loop around the A/D converter.  
• Single Chip QPSK Demodulator with 10kHz Tracking  
Loop  
• Square Root of Raised Cosine (α = 0.4) Matched  
Filtering  
• 2.048 MBPS Reconstructed Output Data Stream  
• Bit Synchronization with 3kHz Loop Bandwidth  
• Internal Equalization for Multipath Distortion  
• 6-Bit Real Input: Digitized 10.7MHz or 2.1MHz IF  
• Level Detection for External IF AGC Loop  
• 0.1s Acquisition Time  
The QPSK demodulator derives all timing from CLKIN. The  
chip divides this clock by 2 to provide the sample clock for the  
external A/D converter. The -27 version operates at a clock  
input of 26.97MHz and demodulates a 10.7MHz QPSK signal  
to recover the 2048 KSPS data. The -25 version operates at a  
clock input of 25.6MHz and demodulates a 2.1MHz QPSK  
signal to recover the 2048 KSPS data. Variation from these  
CLKIN frequencies will progressively degrade the receive  
data rate, the receive IF, acquisition sweep rate, acquisition  
sweep range and loop bandwidths as the deviation increases  
from normal CLKIN. Details on the maximum allowable devia-  
tion are found in the Input Characteristics section. The  
HSP50306 processes 6-bit offset binary data. 4-bit data pro-  
vides adequate performance for many applications.  
-9  
• 10 BER  
• <116mA on +5.0V Supply  
Applications  
• Cable Data Link Receivers  
• Cable Control Channel Receivers  
Ordering Information  
TEMP.  
PKG.  
NO.  
o
PART NUMBER  
HSP50306SC-27  
HSP50306SC-2796  
HSP50306SC-25  
HSP50306SC-2596  
RANGE ( C)  
PACKAGE  
16 Ld SOIC  
0 to 70  
M16.3  
0 to 70  
Tape and Reel  
16 Ld SOIC  
0 to 70  
M16.3  
0 to 70  
Tape and Reel  
Block Diagram  
I
4 TAP  
ADAPTIVE  
EQUALIZER  
Q
6
DIN0-5  
I
DIFF.  
DECODE/  
MUX  
DATAOUT  
COS SIN  
NCO  
Q
BIT PHASE  
DETECTOR  
LEVEL  
AGCOUT  
DETECT  
LOCK  
CARRIER  
PHASE  
DETECT  
ADCLK  
CLKIN  
RESET  
TEST  
LOCK  
DETECT  
TIMING  
GENERATOR  
BIT SYNC  
LOOP FILTER  
CLKOUT  
CARRIER  
LOOP FILTER  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
File Number 4162.2  
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 19989-272  
12345678

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