Datasheet > HSP9501_04

HSP9501_04

更新时间： 2024-02-22 06:07:01

品牌	Logo	应用领域
英特矽尔 - INTERSIL		/
页数	文件大小	规格书
8页	375K
描述
Programmable Data Buffer

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数据手册

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HSP9501_04 数据手册

HSP9501

Data Sheet

Augus t 2004

FN2786.5

Programmable Data Buffer

Features

The HSP9501 is a 10-Bit wide programmable data buffer

designed for use in high speed digital systems. Two different

modes of operation can be selected through the use of the

MODSEL input. In the delay mode, a programmable data

pipeline is created which can provide 2 to 1281 clock cycles

of delay between the input and output data. In the data

recirculate mode, the output data path is internally routed

back to the input to provide a programmable circular buffer.

• DC to 32MHz Operating Frequency

• Programmable Buffer Length from 2 to 1281 Words

• Supports Data Words to 10 Bits

• Clock Select Logic for Positive or Negative Edge

System Clocks

• Data Recirculate or Delay Modes of Operation

• Expandable Data Word Width or Buffer Length

• Three-State Outputs

The length of the buffer or amount of delay is programmed

through the use of the 11-bit Length Control Input Port (LC0-

10) and the Length Control Enable (LCEN). An 11-bit value

is applied to the LC0-10 inputs, LCEN is asserted, and the

next selected clock edge loads the new count value into the

Length Control Register. The delay path of the HSP9501

consists of two registers with a programmable delay RAM

between them, therefore, the value programmed into the

Length Control Register is the desired length - 2. The range

of values which can be programmed into the Length Control

overall range of programmable delays from 2 to 1281.

• TTL Compatible Inputs/Outputs

• Low Power CMOS

Applications

• Sample Rate Conversion

• Data Time Compression/Expansion

• Software Controlled Data Alignment

• Programmable Serial Data Shifting

• Audio/Speech Data Processing Video/Image Processing

Clock select logic is provided to allow the use of a positive or

negative edge system clock as the CLK input to the

HSP9501. The active edge of the CLK input is controlled

through the use of the CLKSEL input. All synchronous timing

(i.e., data setup, hold, and output delays) are relative to the

clock edge selected by CLKSEL. An additional clock enable

input (CLKEN) provides a means of disabling the internal

clock and holding the existing contents temporarily. All

outputs of the HSP9501 are three-state outputs to allow

direct interfacing to system or multi-use buses.

Video/Image Proces s ing

• 1-H Delay Line of 910 NTSC, 1135 PAL or 1280 Samples:

- High Resolution Monitor Delay Line

- Comb Filter Designs

- Progressive Scanning Display

- TV Standards Conversion

- Image Processing

The HSP9501 is recommended for digital video processing

or any applications which require a programmable delay or

circular data buffer.

Ordering Information

TEMP.

PKG.

DWG. #

PART NUMBER

RANGE (°C)

PACKAGE

44 Ld PLCC

HSP9501JC-32

0 to 70

N44.65

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

12 3 4 5 6 7 8

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与HSP9501_04相关器件

型号	品牌	获取价格	描述	数据表
HSP9501JC-25	INTERSIL	获取价格	Programmable Data Buffer
HSP9501JC-2596	INTERSIL	获取价格	Programmable Data Buffer
HSP9501JC-2596	RENESAS	获取价格	10-BIT, DSP-PIPELINE REGISTER, PQCC44
HSP9501JC-30	RENESAS	获取价格	10-BIT, DSP-PIPELINE REGISTER, PQCC44
HSP9501JC-32	INTERSIL	获取价格	Programmable Data Buffer
HSP9501JC-32	RENESAS	获取价格	Programmable Data Buffer; PLCC44; Temp Range: 0° to 70°
HSP9501JC-3296	RENESAS	获取价格	10-BIT, DSP-PIPELINE REGISTER, PQCC44
HSP9520	INTERSIL	获取价格	Multilevel Pipeline Registers
HSP9520CP	INTERSIL	获取价格	Multilevel Pipeline Registers
HSP9520CS	INTERSIL	获取价格	Multilevel Pipeline Registers

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