Datasheet > HSP9501JC-32

HSP9501JC-32

更新时间： 2024-09-08 20:24:23

品牌	Logo	应用领域
瑞萨 - RENESAS		/
页数	文件大小	规格书
8页	50K
描述
Programmable Data Buffer; PLCC44; Temp Range: 0° to 70°

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HSP9501JC-32 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	PLCC	包装说明：	LCC-44
针数：	44	Reach Compliance Code：	not_compliant
ECCN代码：	3A991.A.2	HTS代码：	8542.39.00.01
Factory Lead Time：	1 week	风险等级：	5.76
Is Samacsys：	N	边界扫描：	NO
最大时钟频率：	32 MHz	外部数据总线宽度：	10
JESD-30 代码：	S-PQCC-J44	JESD-609代码：	e0
长度：	16.585 mm	低功率模式：	NO
湿度敏感等级：	4	端子数量：	44
最高工作温度：	70 °C	最低工作温度：
输出数据总线宽度：	10	封装主体材料：	PLASTIC/EPOXY
封装代码：	QCCJ	封装形状：	SQUARE
封装形式：	CHIP CARRIER	峰值回流温度（摄氏度）：	225
认证状态：	Not Qualified	座面最大高度：	4.57 mm
最大供电电压：	5.25 V	最小供电电压：	4.75 V
标称供电电压：	5 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	J BEND
端子节距：	1.27 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	16.585 mm
uPs/uCs/外围集成电路类型：	DSP PERIPHERAL, PIPELINE REGISTER	Base Number Matches：	1

HSP9501JC-32 数据手册

HSP9501

Data Sheet

January 1999

File Number 2786.4

Programmable Data Buffer

Features

The HSP9501 is a 10-Bit wide programmable data buffer

designed for use in high speed digital systems. Two different

modes of operation can be selected through the use of the

MODSEL input. In the delay mode, a programmable data

pipeline is created which can provide 2 to 1281 clock cycles

of delay between the input and output data. In the data

recirculate mode, the output data path is internally routed

back to the input to provide a programmable circular buffer.

• DC to 32MHz Operating Frequency

• Programmable Buffer Length from 2 to 1281 Words

• Supports Data Words to 10 Bits

• Clock Select Logic for Positive or Negative Edge

System Clocks

• Data Recirculate or Delay Modes of Operation

• Expandable Data Word Width or Buffer Length

• Three-State Outputs

The length of the buffer or amount of delay is programmed

through the use of the 11-bit Length Control Input Port (LC0-

10) and the Length Control Enable (LCEN). An 11-bit value

is applied to the LC0-10 inputs, LCEN is asserted, and the

next selected clock edge loads the new count value into the

Length Control Register. The delay path of the HSP9501

consists of two registers with a programmable delay RAM

between them, therefore, the value programmed into the

Length Control Register is the desired length - 2. The range

of values which can be programmed into the Length Control

overall range of programmable delays from 2 to 1281.

• TTL Compatible Inputs/Outputs

• Low Power CMOS

Applications

• Sample Rate Conversion

• Data Time Compression/Expansion

• Software Controlled Data Alignment

• Programmable Serial Data Shifting

• Audio/Speech Data Processing Video/Image Processing

Clock select logic is provided to allow the use of a positive or

negative edge system clock as the CLK input to the

HSP9501. The active edge of the CLK input is controlled

through the use of the CLKSEL input. All synchronous timing

(i.e., data setup, hold, and output delays) are relative to the

clock edge selected by CLKSEL. An additional clock enable

input (CLKEN) provides a means of disabling the internal

clock and holding the existing contents temporarily. All

outputs of the HSP9501 are three-state outputs to allow

direct interfacing to system or multi-use busses.

Video/Image Processing

• 1-H Delay Line of 910 NTSC, 1135 PAL or 1280 Samples:

- High Resolution Monitor Delay Line

- Comb Filter Designs

- Progressive Scanning Display

- TV Standards Conversion

- Image Processing

The HSP9501 is recommended for digital video processing

or any applications which require a programmable delay or

circular data buffer.

Ordering Information

TEMP.

PKG.

NO.

PART NUMBER RANGE ( C)

PACKAGE

44 Ld PLCC

HSP9501JC-25

HSP9501JC-32

HSP9501JC-2596

0 to 70

N44.65

44 Ld PLCC

Tape and Reel

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

3-1

12 3 4 5 6 7 8

中文翻译

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与HSP9501JC-32相关器件

型号	品牌	获取价格	描述	数据表
HSP9501JC-3296	RENESAS	获取价格	10-BIT, DSP-PIPELINE REGISTER, PQCC44
HSP9520	INTERSIL	获取价格	Multilevel Pipeline Registers
HSP9520CP	INTERSIL	获取价格	Multilevel Pipeline Registers
HSP9520CS	INTERSIL	获取价格	Multilevel Pipeline Registers
HSP9520SC	RENESAS	获取价格	8-BIT, DSP-PIPELINE REGISTER, PDSO24
HSP9521	INTERSIL	获取价格	Multilevel Pipeline Registers
HSP9521CP	INTERSIL	获取价格	Multilevel Pipeline Registers
HSP9521CS	INTERSIL	获取价格	Multilevel Pipeline Registers
HSP9521PC	RENESAS	获取价格	8-BIT, DSP-PIPELINE REGISTER, PDIP24
HSP9521SC	RENESAS	获取价格	8-BIT, DSP-PIPELINE REGISTER, PDSO24

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