Datasheet > HSP9521CS

HSP9521CS

更新时间： 2024-11-14 22:48:31

品牌	Logo	应用领域
英特矽尔 - INTERSIL		外围集成电路光电二极管输出元件
页数	文件大小	规格书
4页	28K
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Multilevel Pipeline Registers

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HSP9521CS 数据手册

HSP9520, HSP9521

Data Sheet

May 1999

File Number 2811.5

Multilevel Pipeline Registers

Features

These devices are multilevel pipeline registers implemented

using a low power CMOS process. They are pin for pin

compatible replacements for industry standard multilevel

pipeline registers such as the L29C520 and L29C521. The

HSP9520 and HSP5921 are direct replacements for the

AM29520 and AM29521 and WS59520 and WS59521.

• Four 8-Bit Registers

• Hold, Transfer and Load Instructions

• Single 4-Stage or Dual-2 Stage Pipelining

• All Register Contents Available at Output

• Fully TTL Compatible

They consist of four 8-bit registers which are dual ported.

They can be conﬁgured as a single four level pipeline or a

dual two level pipeline. A single 8-bit input is provided, and

the pipelining conﬁguration is determined by the instruction

code input to the I0 and I1 inputs (see instruction control).

• Three-State Outputs

• High Speed, Low Power CMOS

Applications

The contents of any of the four registers is selectable at the

multiplexed outputs through the use of the S0 and S1

multiplexer control inputs (see register select. The output is 8

bits wide and is three-stated through the use of the OE input.

• Array Processor

• Digital Signal Processor

• A/D Buffer

• Telecommunication

• Byte Wide Shift Register

• Mainframe Computers

The HSP9520 and HSP9521 differ only in the way data is

loaded into and between the registers in dual two-level

operation. In the HSP9520 when data is loaded into the ﬁrst

level the existing data in the ﬁrst level is moved to the second

level. In the HSP9521 loading the ﬁrst level simply causes

the current data to be overwritten. Transfer of data to the

second level is achieved using the single four level mode (I1,

I0 = ‘0’). This instruction also causes the ﬁrst level to be

loaded. The HOLD instruction (I1, I0 = ‘1’) provides a means

of holding the contents of all registers.

Pinout

HSP9520, HSP9521 (SOIC, PDIP)

TOP VIEW

24 V

23 S0

22 S1

21 Y0

20 Y1

19 Y2

18 Y3

17 Y4

16 Y5

15 Y6

14 Y7

13 OE

Ordering Information

TEMP.

PKG.

NO.

PART NUMBER RANGE ( C)

PACKAGE

24 Ld PDIP

HSP9520CP

HSP9520CS

HSP9521CP

HSP9521CS

0 to 70

E24.3

24 Ld SOIC

24 Ld PDIP

24 Ld SOIC

M24.3

E24.3

M24.3

D7 10

CLK 11

GND 12

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

12 3 4

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