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HSP50415EVAL1

更新时间: 2024-11-14 22:18:07
品牌 Logo 应用领域
英特矽尔 - INTERSIL /
页数 文件大小 规格书
5页 43K
描述
HSP50415EVAL1 Evaluation Kit

HSP50415EVAL1 数据手册

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HSP50415EVAL1  
TM  
Data Sheet  
April 2000  
File Number 4859  
HSP50415EVAL1 Evaluation Kit  
Features  
The HSP50415EVAL1 is an evaluation kit for the HSP50415  
wideband programmable modulator. The kit consists of an  
evaluation Circuit Card Assembly (CCA) complete with the  
HSP50415 device and additional circuitry to provide for  
control via a computer parallel port. Windows based  
demonstration software is provided for full user  
programmability and control of all HSP50415 operational  
modes. The evaluation board provides digital outputs which  
are accessible through a standard logic analyzer header. It  
also provides both single ended and differential analog  
outputs via standard SMA connectors. Documentation  
includes a user’s manual, full evaluation board schematics  
and PCB layout materials. Special filter files, pattern files  
and example configuration script files are included for quickly  
configuring the board.  
• Evaluation CCA Complete With HSP50415 Wideband  
Programmable Modulator  
• Windows Based Demonstration Software  
• Example Files For Common Modulation Techniques  
Reference Documents  
• HSP50415EVAL1 Demonstration Software in File  
HSP50415.exe  
• Example Configuration Files in *.js, filter files in *.coe, and  
Pattern Files in *.pat  
• HSP50415EVAL1 Schematics in File sch415bx.pdf  
• HSP50415EVAL1 Layout in File fab415bx.pdf  
• HSP50415EVAL1 Bill of Material in File bom415bx.pdf  
The latest version for all reference materials and programs is  
available via the Intersil internet website:  
‘www.intersil.com/commlink/download/hsp50415eval1’.  
Block Diagram  
COMPUTER  
PARALLEL  
PORT  
/4  
D3-D6 STATUS  
LEDs  
P1 25 PIN ‘D’  
LPT PORT  
U2  
U4  
CY37256V CPLD  
HSP50415 WIDEBAND PROG. MOD.  
STATUS /4  
FEMPT, FOVRFL, FFULL LOCKDET  
CE, WR, RD, RESET, ADDR<2:0>, INTREQ  
CDATA<7:0>  
CONTROL /8  
J15 TEST  
SOCKET  
U1  
LVX161284  
IEEE XCVR  
P3 TEST  
HEADER  
U3  
TXEN  
ISTRB  
DIN<15:0>  
CONTROL /3  
I OUT<13:0>  
J13 TEST  
SOCKET  
ALVCH16823  
DATA REG  
IOUTA  
J2  
J14 TEST  
SOCKET  
T1  
I OUT  
SMA  
U7  
CY7C1327  
SRAM  
DATA /18  
CONTROL /7  
ADDRESS /20  
IOUTB  
/17  
U8  
HC244  
BUFFER  
DATACLK  
SYSCLK/2  
2XSYSCLK  
QOUTA  
QOUTB  
J3  
SMA  
REFCLK  
CLK  
T2  
Q OUT  
JTAG /6  
PLLRC  
P5 JTAG  
HEADER  
DEBUG /16  
U6  
OSC  
P2 DEBUG  
HEADER  
U5  
OSC  
J5  
SMA  
J4  
SMA  
LOOP  
FILTER  
EXTERNAL CLK  
EXTERNAL CLK  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright © Intersil Corporation 2000  
4-1  

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