HSP50214
Programmable Downconverter
February 2000
[ /Title
(HSP5
0214)
/Sub-
ject
(Pro-
gram-
mable
Down-
con-
verter)
/Autho
r ()
/Key-
words
(Inter-
sil
Semi-
con-
ductor,
Down-
con-
verter,
Down
Con-
verter,
Pro-
Features
Description
• Up to 52 MSPS Front-End Processing Rates (CLKIN)
and 35 MSPS Back-End Processing Rates (PROCCLK) digitized IF data into filtered baseband data which can be
Clocks May Be Asynchronous
The HSP50214 Programmable Downconverter converts
processed by a standard DSP microprocessor. The
Programmable Downconverter (PDC) performs down
conversion, decimation, narrowband low pass filtering, gain
scaling, re-sampling, and Cartesian to Polar coordinate
conversion.
• Processing Capable of >100dB SFDR8-
• Up to 255-Tap Programmable FIR
• Overall Decimation Factor Ranging from 4 to 16384
• Output Samples Rates to 8.2 MSP8-S with Output
Bandwidths to 625kHz Lowpass
The 14-bit sampled IF input is down converted to baseband
by digital mixers and a quadrature NCO, as shown in the
Block Diagram. A decimating (4 to 32) fifth order Cascaded
Integrator-Comb (CIC) filter can be applied to the data
before it is processed by up to 5 decimate-by-2 halfband fil-
ters. The halfband filters are followed by a 255-tap program-
mable FIR filter. The output data from the programmable FIR
filter is scaled by a digital AGC before being re-sampled in a
polyphase FIR filter. The output section can provide seven
types of data: Cartesian (I, Q), polar (R, θ), filtered frequency
(dθ/dt), timing error (TE), and AGC level in either parallel or
serial format.
• 32-Bit Programmable NCO for Channel Selection and
Carrier Tracking
• Digital Re-Sampling Filter for Symbol Tracking Loops
and Incommensurate Sample-to-Output Clock Ratios
• Digital AGC with Programmable Limits and Sle8- Rate
to Optimize Output Signal Resolution; Fixed or Auto
Gain Adjust
• Serial, Parallel, and FIFO 16-Bit Output Modes
• Cartesian to Polar Converter and Frequency Discrimi-
nator for AFC Loops and Demodulation of AM, FM,
FSK, and DPSK
Ordering Information
• Input Level Detector for External I.F. AGC Support
PART
NUMBER
TEMP.
RANGE ( C)
o
PACKAGE
120 Ld MQFP
120 Ld MQFP
PKG. NO.
Q120.28x28
Q120.28x28
Applications
HSP50214VC
HSP50214VI
0 to 70
• Single Channel Digital Software Radio Receivers
• Base Station Rx’s: AMPS, NA TDMA, GSM, and CDMA
-40 to 85
• Compatible with HSP50210 Digital Costas Loop for
PSK Reception
• Evaluation Platform Available
gram-
mable
Down-
con-
verter,
DSP,
AMPS,
TDMA
,
North
Ameri-
can
Block Diagram
MICROPROCESSOR
READ/WRITE
CONTROL
C(7:0)
AGC LOOP FILTER
AGC
LEVEL DETECT
I SYMBOL
TH
5
ORDER
CIC
FILTER
POLYPHASE
FIR AND
HALFBAND
FILTERS
SEROUTA
SEROUTB
AOUT(15:0)
CARTESIAN
MAG.
TO
POLAR
IN(13:0)
PHASE
COORDINATE
CONVERTER
TH
5
ORDER
CIC
FILTER
BOUT(15:0)
POLYPHASE
FIR AND
GAIN
ADJ
(2:0)
HALFBAND
FILTERS
Q SYMBOL
CARRIER
NCO
COF
FREQ
SOF
CLKIN
DISCRIMINATOR
RE-SAMPLING
NCO
PROCCLK
REFCLK
TIMING ERROR
∆
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
File Number 4266.3
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 2000
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