HSP50214A
Programmable Downconverter
December 1999
[ /Title
(HSP5
0214A
)
/Sub-
ject (
Features
Description
• Up to 65 MSPS Front-End Processing Rates (CLKIN) and
55 MSPS (41 MSPS Using the Discriminator) Back-End
Processing Rates (PROCCLK)
The HSP50214A Programmable Downconverter converts dig-
itized IF data into filtered baseband data which can be pro-
cessed by
a
standard DSP microprocessor. The
Clocks May Be Asynchronous
Programmable Downconverter (PDC) performs down conver-
sion, decimation, narrowband low pass filtering, gain scaling,
resampling, and Cartesian to Polar coordinate conversion.
• Processing Capable of >100dB SFDR
• Up to 255-Tap Programmable FIR
Pro-
• Overall Decimation Factor Ranging from 4 to 16384
gram-
mable
Down-
con-
verter)
/Autho
r ()
/Key-
words
(Inter-
sil
Semi-
con-
ductor,
Down-
con-
verter,
Down
Con-
The 14-bit sampled IF input is down converted to baseband
by digital mixers and a quadrature NCO, as shown in the
Block Diagram. A decimating (4 to 32) fifth order Cascaded
Integrator-Comb (CIC) filter can be applied to the data
before it is processed by up to 5 decimate-by-2 halfband fil-
ters. The halfband filters are followed by a 255-tap pro-
grammable FIR filter. The output data from the
programmable FIR filter is scaled by a digital AGC before
being re-sampled in a polyphase FIR filter. The output sec-
tion can provide seven types of data: Cartesian (I, Q), polar
(R, q), filtered frequency (dq/dt), Timing Error (TE), and
AGC level in either parallel or serial format.
• Output Samples Rates to 12.94 MSPS with Output Band-
widths to 982kHz Lowpass
• 32-Bit Programmable NCO for Channel Selection and Car-
rier Tracking
• Digital Resampling Filter for Symbol Tracking Loops and
Incommensurate Sample-to-Output Clock Ratios
• Digital AGC with Programmable Limits and Slew Rate to
Optimize Output Signal Resolution; Fixed or Auto Gain
Adjust
• Serial, Parallel, and FIFO 16-Bit Output Modes
• Cartesian to Polar Converter and Frequency Discriminator
for AFC Loops and Demodulation of AM, FM, FSK, and
DPSK
Ordering Information
• Input Level Detector for External I.F. AGC Support
PART
NUMBER
TEMP.
RANGE ( C)
o
PACKAGE
120 Ld MQFP
120 Ld MQFP
PKG. NO.
Q120.28x28
Q120.28x28
Applications
HSP50214AVC
HSP50214AVI
0 to 70
• Single Channel Digital Software Radio Receivers
• Base Station Rx’s: AMPS, NA TDMA, GSM, and CDMA
-40 to 85
• Compatible with HSP50210 Digital Costas Loop for PSK
Reception
• Evaluation Platform Available
verter,
Pro-
Block Diagram
gram-
mable
Down-
con-
verter,
DSP,
MICROPROCESSOR
READ/WRITE
CONTROL
C(7:0)
AGC LOOP FILTER
AGC
LEVEL DETECT
I OUT
TH
5
ORDER
CIC
FILTER
POLYPHASE
FIR AND
SEROUTA
SEROUTB
AOUT(15:0)
CARTESIAN
TO
MAG.
HALFBAND
FILTERS
AMPS,
TDMA
, North
Ameri-
can
POLAR
IN(13:0)
PHASE
COORDINATE
CONVERTER
TH
5
ORDER
CIC
FILTER
BOUT(15:0)
POLYPHASE
FIR AND
HALFBAND
FILTERS
GAIN
ADJ
(2:0)
Q OUT
CARRIER
NCO
COF
FREQ
SOF
CLKIN
DISCRIMINATOR
RESAMPLING
NCO
TIMING ERROR
PROCCLK
REFCLK
∆
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
File Number 4449.1
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
1