Datasheet > HSP50306SC-2596

HSP50306SC-2596

更新时间： 2024-11-14 22:21:15

品牌	Logo	应用领域
英特矽尔 - INTERSIL		电信集成电路光电二极管
页数	文件大小	规格书
8页	41K
描述
Digital QPSK Demodulator

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

HSP50306SC-2596 数据手册

HSP50306

Digital QPSK Demodulator

February 1998

Features

Description

• 25.6MHz or 26.97MHz Clock Rates

The HSP50306 is a 6-bit QPSK demodulator chip designed

for use in high signal to noise environments which have some

multipath distortion. The part recovers 2.048 MBPS data from

samples of a QPSK modulated 10.7MHz or 2.1MHz carrier.

The chip coherently demodulates the waveform, recovers

symbol timing, adaptively equalizes the signal to remove

multipath distortion, differentially decodes and multiplexes the

data decisions. 8-A lock signal is provided to indicate when

the tracking loops are locked and the data decisions are valid.

To optimize performance, a gain error feedback signal is

provided which can be ﬁltered and used to close an I.F. AGC

loop around the A/D converter.

• Single Chip QPSK Demodulator with 10kHz Tracking

Loop

• Square Root of Raised Cosine (α = 0.4) Matched

Filtering

• 2.048 MBPS Reconstructed Output Data Stream

• Bit Synchronization with 3kHz Loop Bandwidth

• Internal Equalization for Multipath Distortion

• 6-Bit Real Input: Digitized 10.7MHz or 2.1MHz IF

• Level Detection for External IF AGC Loop

• 0.1s Acquisition Time

The QPSK demodulator derives all timing from CLKIN. The

chip divides this clock by 2 to provide the sample clock for the

external A/D converter. The -27 version operates at a clock

input of 26.97MHz and demodulates a 10.7MHz QPSK signal

to recover the 2048 KSPS data. The -25 version operates at a

clock input of 25.6MHz and demodulates a 2.1MHz QPSK

signal to recover the 2048 KSPS data. Variation from these

CLKIN frequencies will progressively degrade the receive

data rate, the receive IF, acquisition sweep rate, acquisition

sweep range and loop bandwidths as the deviation increases

from normal CLKIN. Details on the maximum allowable devia-

tion are found in the Input Characteristics section. The

HSP50306 processes 6-bit offset binary data. 4-bit data pro-

vides adequate performance for many applications.

-9

• 10 BER

• <116mA on +5.0V Supply

Applications

• Cable Data Link Receivers

• Cable Control Channel Receivers

Ordering Information

TEMP.

PKG.

NO.

PART NUMBER

HSP50306SC-27

HSP50306SC-2796

HSP50306SC-25

HSP50306SC-2596

RANGE ( C)

PACKAGE

16 Ld SOIC

0 to 70

M16.3

0 to 70

Tape and Reel

16 Ld SOIC

0 to 70

M16.3

0 to 70

Tape and Reel

Block Diagram

4 TAP

ADAPTIVE

EQUALIZER

DIN0-5

DIFF.

DECODE/

MUX

DATAOUT

COS SIN

NCO

BIT PHASE

DETECTOR

LEVEL

AGCOUT

DETECT

LOCK

CARRIER

PHASE

DETECT

ADCLK

CLKIN

RESET

TEST

LOCK

DETECT

TIMING

GENERATOR

BIT SYNC

LOOP FILTER

CLKOUT

CARRIER

LOOP FILTER

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

File Number 4162.2

12 3 4 5 6 7 8

中文翻译

下载PDF

与HSP50306SC-2596相关器件

型号	品牌	获取价格	描述	数据表
HSP50306SC-27	INTERSIL	获取价格	Digital QPSK Demodulator
HSP50306SC-2796	INTERSIL	获取价格	Digital QPSK Demodulator
HSP50307	INTERSIL	获取价格	Burst QPSK Modulator
HSP50307_00	INTERSIL	获取价格	Burst QPSK Modulator
HSP50307EVAL1	INTERSIL	获取价格	2.0GHz to 2.7GHz DownConverter
HSP50307SC	INTERSIL	获取价格	Burst QPSK Modulator
HSP50415	INTERSIL	获取价格	Wideband Programmable Modulator (WPM)
HSP50415_07	INTERSIL	获取价格	Wideband Programmable Modulator (WPM)
HSP50415EVAL1	INTERSIL	获取价格	HSP50415EVAL1 Evaluation Kit
HSP50415VI	INTERSIL	获取价格	Wideband Programmable Modulator (WPM)

与HSP50306SC-2596相关文章

解析光耦仿真器：升级光耦合器技术的必要性
2024-11-18

7
英伟达新一代Blackwell GPU过热问题致交付延迟
2024-11-18

4
国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
2024-11-14

30
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
2024-11-14

13

产品中心

服务支持

精选活动

关于我们

帮助中心

HSP50306SC-2596

HSP50306SC-2596 数据手册

与HSP50306SC-2596相关器件

与HSP50306SC-2596相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

HSP50306SC-2596

HSP50306SC-2596 数据手册

与HSP50306SC-2596相关器件

与HSP50306SC-2596相关文章

您还可以找

您在本页遇到什么问题？