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HSP50210JI-52

更新时间： 2024-02-25 19:14:38
品牌 Logo 应用领域
英特矽尔 - INTERSIL 电信集成电路
页数 文件大小 规格书
49页 328K
描述
Digital Costas Loop

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中文翻译

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HSP50210JI-52 技术参数

是否Rohs认证：符合生命周期：Obsolete
零件包装代码：PLCC包装说明：QCCJ, LDCC84,1.2SQ
针数：84Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：5.65
Is Samacsys：NJESD-30 代码：S-PQCC-J84
JESD-609代码：e3长度：29.31 mm
湿度敏感等级：4功能数量：1
端子数量：84最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：QCCJ封装等效代码：LDCC84,1.2SQ
封装形状：SQUARE封装形式：CHIP CARRIER
峰值回流温度（摄氏度）：245电源：5 V
认证状态：Not Qualified座面最大高度：4.57 mm
子类别：Other Telecom ICs最大压摆率：0.225 mA
标称供电电压：5 V表面贴装：YES
电信集成电路类型：TELECOM CIRCUIT温度等级：INDUSTRIAL
端子面层：Matte Tin (Sn) - annealed端子形式：J BEND
端子节距：1.27 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：29.31 mm
Base Number Matches：1

HSP50210JI-52 数据手册

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HSP50210  
Data Sheet  
January 1999  
File Number 3652.4  
Digital Costas Loop  
Features  
The Digital Costas Loop (DCL) performs many of the  
baseband processing tasks required for the demodulation of  
BPSK, QPSK, 8-PSK, OQPSK, FSK, AM and FM  
waveforms. These tasks include matched filtering, carrier  
tracking, symbol synchronization, AGC, and soft decision  
slicing. The DCL is designed for use with the HSP50110  
Digital Quadrature Tuner to provide a two chip solution for  
digital down conversion and demodulation.  
• Clock Rates Up to 52MHz  
• Selectable Matched Filtering with Root Raised Cosine or  
Integrate and Dump Filter  
• Second Order Carrier and Symbol Tracking Loop  
Filters  
• Automatic Gain Control (AGC)  
• Discriminator for FM/FSK Detection and Discriminator  
Aided Acquisition  
The DCL processes the In-phase (I) and quadrature (Q)  
components of a baseband signal which have been digitized  
to 10 bits. As shown in the block diagram, the main signal  
path consists of a complex multiplier, selectable matched  
filters, gain multipliers, cartesian-to-polar converter, and soft  
decision slicer. The complex multiplier mixes the I and Q  
inputs with the output of a quadrature NCO. Following the  
mix function, selectable matched filters are provided which  
perform integrate and dump or root raised cosine filtering  
(α ~ 0.40). The matched filter output is routed to the slicer,  
which generates 3-bit soft decisions, and to the cartesian-to-  
polar converter, which generates the magnitude and phase  
terms required by the AGC and Carrier Tracking Loops.  
• Swept Acquisition with Programmable Limits  
• Lock Detector  
• Data Quality and Signal Level Measurements  
• Cartesian to Polar Converter  
• 8-Bit Microprocessor Control - Status Interface  
• Designed to work with the HSP50110 Digital  
Quadrature Tuner  
• 84 Lead PLCC  
Applications  
The PLL system solution is completed by the HSP50210  
error detectors and second order Loop Filters that provide  
carrier tracking and symbol synchronization signals. In  
applications where the DCL is used with the HSP50110,  
these control loops are closed through a serial interface  
between the two parts. To maintain the demodulator  
performance with varying signal power and SNR, an internal  
AGC loop is provided to establish an optimal signal level at  
the input to the slicer and to the cartesian-to-polar converter.  
• Satellite Receivers and Modems  
• BPSK, QPSK, 8-PSK, OQPSK, FSK, AM and FM  
Demodulators  
• Digital Carrier Tracking  
• Related Products: HSP50110 Digital Quadrature Tuner,  
D/A Converters HI5721, HI5731, HI5741  
• HSP50110/210EVAL Digital Demod Evaluation Board  
Block Diagram  
CARRIER  
TRACK  
CONTROL  
(COF)  
CARRIER ACQ/TRK  
LOOP FILTER  
CARRIER PHASE  
ERROR DETECT  
LOCK  
DETECT  
LKINT  
LEVEL  
HI/LO  
NCO  
SIN  
LOOP  
LEVEL  
DETECT  
THRESH  
FILTER  
DETECT  
COS  
A
10  
I SER OR  
OUT(9-0)  
10  
MAGNITUDE  
I
8
RRC  
FILTER  
8
8
I
(9-0)  
IN  
INTEGRATE/  
DUMP  
CARTESIAN  
TO  
POLAR  
PHASE  
3
SERCLK  
OR CLK  
8
10  
INTEGRATE/  
DUMP  
10  
Q SER OR  
Q
RRC  
FILTER  
3
SLICER  
Q
(9-0)  
IN  
B
OUT(9-0)  
Q
SYMBOL  
TRACK  
(SOF)  
SYMBOL  
PHASE  
ERROR  
DETECT  
I
SYMBOL  
SMBLCLK  
CONTROL  
TRACKING  
LOOP FILTER  
CONTROL/  
STATUS  
BUS  
OEA  
OEB  
13  
CONTROL  
INTERFACE  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999  
3-253  
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