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HSP50210

更新时间: 2024-01-30 08:15:40
品牌 Logo 应用领域
英特矽尔 - INTERSIL /
页数 文件大小 规格书
49页 328K
描述
Digital Costas Loop

HSP50210 技术参数

生命周期:Obsolete包装说明:,
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.66JESD-30 代码:S-PQCC-J84
功能数量:1端子数量:84
封装主体材料:PLASTIC/EPOXY封装形状:SQUARE
封装形式:CHIP CARRIER认证状态:Not Qualified
表面贴装:YES电信集成电路类型:TELECOM CIRCUIT
端子形式:J BEND端子位置:QUAD
Base Number Matches:1

HSP50210 数据手册

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HSP50210  
Data Sheet  
January 1999  
File Number 3652.4  
Digital Costas Loop  
Features  
The Digital Costas Loop (DCL) performs many of the  
baseband processing tasks required for the demodulation of  
BPSK, QPSK, 8-PSK, OQPSK, FSK, AM and FM  
waveforms. These tasks include matched filtering, carrier  
tracking, symbol synchronization, AGC, and soft decision  
slicing. The DCL is designed for use with the HSP50110  
Digital Quadrature Tuner to provide a two chip solution for  
digital down conversion and demodulation.  
• Clock Rates Up to 52MHz  
• Selectable Matched Filtering with Root Raised Cosine or  
Integrate and Dump Filter  
• Second Order Carrier and Symbol Tracking Loop  
Filters  
• Automatic Gain Control (AGC)  
• Discriminator for FM/FSK Detection and Discriminator  
Aided Acquisition  
The DCL processes the In-phase (I) and quadrature (Q)  
components of a baseband signal which have been digitized  
to 10 bits. As shown in the block diagram, the main signal  
path consists of a complex multiplier, selectable matched  
filters, gain multipliers, cartesian-to-polar converter, and soft  
decision slicer. The complex multiplier mixes the I and Q  
inputs with the output of a quadrature NCO. Following the  
mix function, selectable matched filters are provided which  
perform integrate and dump or root raised cosine filtering  
(α ~ 0.40). The matched filter output is routed to the slicer,  
which generates 3-bit soft decisions, and to the cartesian-to-  
polar converter, which generates the magnitude and phase  
terms required by the AGC and Carrier Tracking Loops.  
• Swept Acquisition with Programmable Limits  
• Lock Detector  
• Data Quality and Signal Level Measurements  
• Cartesian to Polar Converter  
• 8-Bit Microprocessor Control - Status Interface  
• Designed to work with the HSP50110 Digital  
Quadrature Tuner  
• 84 Lead PLCC  
Applications  
The PLL system solution is completed by the HSP50210  
error detectors and second order Loop Filters that provide  
carrier tracking and symbol synchronization signals. In  
applications where the DCL is used with the HSP50110,  
these control loops are closed through a serial interface  
between the two parts. To maintain the demodulator  
performance with varying signal power and SNR, an internal  
AGC loop is provided to establish an optimal signal level at  
the input to the slicer and to the cartesian-to-polar converter.  
• Satellite Receivers and Modems  
• BPSK, QPSK, 8-PSK, OQPSK, FSK, AM and FM  
Demodulators  
• Digital Carrier Tracking  
• Related Products: HSP50110 Digital Quadrature Tuner,  
D/A Converters HI5721, HI5731, HI5741  
• HSP50110/210EVAL Digital Demod Evaluation Board  
Block Diagram  
CARRIER  
TRACK  
CONTROL  
(COF)  
CARRIER ACQ/TRK  
LOOP FILTER  
CARRIER PHASE  
ERROR DETECT  
LOCK  
DETECT  
LKINT  
LEVEL  
HI/LO  
NCO  
SIN  
LOOP  
LEVEL  
DETECT  
THRESH  
FILTER  
DETECT  
COS  
A
10  
I SER OR  
OUT(9-0)  
10  
MAGNITUDE  
I
8
RRC  
FILTER  
8
8
I
(9-0)  
IN  
INTEGRATE/  
DUMP  
CARTESIAN  
TO  
POLAR  
PHASE  
3
SERCLK  
OR CLK  
8
10  
INTEGRATE/  
DUMP  
10  
Q SER OR  
Q
RRC  
FILTER  
3
SLICER  
Q
(9-0)  
IN  
B
OUT(9-0)  
Q
SYMBOL  
TRACK  
(SOF)  
SYMBOL  
PHASE  
ERROR  
DETECT  
I
SYMBOL  
SMBLCLK  
CONTROL  
TRACKING  
LOOP FILTER  
CONTROL/  
STATUS  
BUS  
OEA  
OEB  
13  
CONTROL  
INTERFACE  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999  
3-253  

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