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HSP50016JC-52

更新时间： 2024-02-24 05:24:02
品牌 Logo 应用领域
英特矽尔 - INTERSIL 外围集成电路时钟
页数 文件大小 规格书
31页 211K
描述
Digital Down Converter

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HSP50016JC-52 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：PLCC包装说明：PLASTIC, LCC-44
针数：44Reach Compliance Code：not_compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
Factory Lead Time：1 week风险等级：5.77
其他特性：TTL COMPATIBLE边界扫描：YES
最大时钟频率：52.6 MHz外部数据总线宽度：16
JESD-30 代码：S-PQCC-J44JESD-609代码：e0
长度：16.585 mm低功率模式：YES
湿度敏感等级：1端子数量：44
最高工作温度：70 °C最低工作温度：
输出数据总线宽度：2封装主体材料：PLASTIC/EPOXY
封装代码：QCCJ封装形状：SQUARE
封装形式：CHIP CARRIER峰值回流温度（摄氏度）：225
认证状态：Not Qualified座面最大高度：4.57 mm
最大供电电压：5.25 V最小供电电压：4.75 V
标称供电电压：5 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：J BEND
端子节距：1.27 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：16.585 mm
uPs/uCs/外围集成电路类型：DSP PERIPHERAL, MIXER

HSP50016JC-52 数据手册

 浏览型号HSP50016JC-52的Datasheet PDF文件第2页浏览型号HSP50016JC-52的Datasheet PDF文件第3页浏览型号HSP50016JC-52的Datasheet PDF文件第4页浏览型号HSP50016JC-52的Datasheet PDF文件第5页浏览型号HSP50016JC-52的Datasheet PDF文件第6页浏览型号HSP50016JC-52的Datasheet PDF文件第7页 
HSP50016  
Data Sheet  
February 1999  
File Number 3288.6  
Digital Down Converter  
Features  
The Digital Down Converter (DDC) is a single chip  
synthesizer, quadrature mixer and lowpass filter. Its input  
data is a sampled data stream of up to 16 bits in width and  
up to a 75 MSPS data rate. The DDC performs down  
conversion, narrowband low pass filtering and decimation to  
produce a baseband signal.  
• 75 MSPS Input Data Rate  
• 16-Bit Data Input; Offset Binary or 2’s Complement  
Format  
• Spurious Free Dynamic Range Through Modulator  
>102dB  
• Frequency Selectivity: <0.006Hz  
• Identical Lowpass Filters for I and Q  
• Passband Ripple: <0.04dB  
The internal synthesizer can produce a variety of signal  
formats. They are: CW, frequency hopped, linear FM up  
chirp, and linear FM down chirp. The complex result of the  
modulation process is lowpass filtered and decimated with  
identical real filters in the in-phase (I) and quadrature (Q)  
processing chains.  
• Stopband Attenuation: >104dB  
• Filter -3dB to -102dB Shape Factor: <1.5  
• Decimation Factors from 32 to 131,072  
• IEEE 1149.1 Test Access Port  
Lowpass filtering is accomplished via a High Decimation  
Filter (HDF) followed by a fixed Finite Impulse Response  
(FIR) filter. The combined response of the two stage filter  
results in a -3dB to -102dB shape factor of better than 1.5.  
The stopband attenuation is greater than 106dB. The  
composite passband ripple is less than 0.04dB. The  
synthesizer and mixer can be bypassed so that the chip  
operates as a single narrow band low pass filter.  
• HSP50016-EV Evaluation Board Available  
Applications  
• Cellular Base Stations  
• Smart Antennas  
• Channelized Receivers  
• Spectrum Analysis  
The chip receives forty bit serial commands as a control  
input. This interface is compatible with the serial I/O port  
available on most microprocessors.  
• Related Products: HI5703, HI5746, HI5766 A/Ds  
The output data can be configured in fixed point or single  
precision floating point. The fixed point formats are 16,  
24, 32, or 38-bit, two’s complement, signed magnitude, or  
offset binary.  
Ordering Information  
PART  
NUMBER  
TEMP. RANGE  
PKG.  
NO.  
o
( C)  
PACKAGE  
44 Ld PLCC  
44 Ld PLCC  
48 Ld CPGA  
HSP50016JC-52  
HSP50016JC-75  
HSP50016GC-52  
0 to 70  
0 to 70  
0 to 70  
N44.65  
N44.65  
G48.A  
The circuit provides an IEEE 1149.1 Test Access Port.  
Block Diagram  
16  
I
HIGH DECIMATION  
LOW PASS FIR  
FILTER  
DATA  
CLK  
I
FILTER  
OUTPUT  
Q
Q
HIGH DECIMATION  
FILTER  
LOW PASS FIR  
FILTER  
COS  
CONTROL  
SIN  
IQSTRB  
COMPLEX  
SINUSOID  
GENERATOR  
CLK  
4R  
CLK  
CLK  
R
IQCLK  
OR  
CLK  
2R  
TEST ACCESS  
PORT  
TEST ACCESS  
PORT/CTRL  
CLK  
SER  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999  
3-198  
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