Datasheet > HSP45256GM-20/883

HSP45256GM-20/883

更新时间： 2024-02-05 11:21:47

品牌	Logo	应用领域
英特矽尔 - INTERSIL		外围集成电路时钟
页数	文件大小	规格书
9页	198K
描述
Binary Correlator

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技术参数
数据手册

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HSP45256GM-20/883 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
包装说明：	PGA, PGA84M,11X11	Reach Compliance Code：	unknown
ECCN代码：	3A001.A.2.C	HTS代码：	8542.39.00.01
风险等级：	5.64	Is Samacsys：	N
边界扫描：	NO	最大时钟频率：	20 MHz
外部数据总线宽度：	8	JESD-30 代码：	S-CPGA-P85
JESD-609代码：	e0	低功率模式：	NO
端子数量：	85	最高工作温度：	125 °C
最低工作温度：	-55 °C	输出数据总线宽度：	8
封装主体材料：	CERAMIC, METAL-SEALED COFIRED	封装代码：	PGA
封装等效代码：	PGA84M,11X11	封装形状：	SQUARE
封装形式：	GRID ARRAY	电源：	5 V
认证状态：	Not Qualified	筛选级别：	38535Q/M;38534H;883B
子类别：	DSP Peripherals	最大压摆率：	140 mA
最大供电电压：	5.5 V	最小供电电压：	4.5 V
标称供电电压：	5 V	表面贴装：	NO
技术：	CMOS	温度等级：	MILITARY
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	PIN/PEG
端子节距：	2.54 mm	端子位置：	PERPENDICULAR
uPs/uCs/外围集成电路类型：	DSP PERIPHERAL, CORRELATOR	Base Number Matches：	1

HSP45256GM-20/883 数据手册

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HSP45256/883

December 1999

Binary Correlator

Features

Description

• This Circuit is Processed in Accordance to MIL-STD- The Intersil HSP45256/883 is a high-speed, 256 tap binary

883 and is Fully Conformant Under the Provisions of correlator. It can be configured to perform one-dimensional

Paragraph 1.2.1.

or two-dimensional correlations of selectable data precision

and length. Multiple HSP45256’s can be cascaded for

increased correlation length. Unused taps can be masked

out for reduced correlation length.

• Reconfigurable 256 Stage Binary Correlator

• 1-Bit Reference x 1, 2, 4, or 8-Bit Data

• Separate Control and Reference Interfaces

• Configurable for 1-D and 2-D Operation

• Double Buffered Mask and Reference

• Programmable Output Delay

The correlation array consists of eight 32-tap stages. These

may be cascaded internally to compare 1, 2, 4 or 8-bit input

data with a 1-bit reference. Depending on the number of bits

in the input data, the length of the correlation can be up to

256, 128, 64, or 32 taps. The HSP45256 can also be

configured as two separate correlators with window sizes

from 4 by 32 to 1 by 128 each. The Mask Register can be

used to prevent any subset of the 256 bits from contributing

to the correlation score.

• Cascadable

• Standard Microprocessor Interface

Applications

• Radar/Sonar

The9- output of the correlation array (correlation score)

feeds the weight and sum logic, which gives added flexibility

to the data format. In addition, an offset register is provided

so that a preprogrammed value can be added to the correla-

tion score. This result is then passed through a user pro-

grammable delay stage to the cascade summer. The delay

stage simplifies the cascading of multiple correlators by

compensating for the latency of previous correlators.

• Spread Spectrum Communications

• Pattern/Character Recognition

• Error Correction Coding

Ordering Information

TEMP.

PKG.

NO.

PART NUMBER

HSP45256GM-20/883

HSP45256GM-25/883

RANGE ( C)

-55 to 125

PACKAGE

85 Ld CPGA

The Binary Correlator is configured by writing a set of control

registers via a standard microprocessor interface. To simplify

operation, both the Control and Reference Registers are

double buffered. This allows the user to load new mask and

reference data while the current correlation is in progress.

G85.A

Block Diagram

DOUT0-7

DIN0-7

256 TAP

CORRELATION

ARRAY

AUXOUT0-8

MUX

DREF0-7

WEIGHT

AND SUM

DCONT0-7

A0-2

CASCADE

SUMMER

DELAY

CONTROL

CASOUT0-12

CASIN0-12

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc.

FN2997.4

12 3 4 5 6 7...9

中文翻译

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