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HSP48212 PDF预览

HSP48212

更新时间: 2024-02-18 00:14:38
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英特矽尔 - INTERSIL /
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9页 61K
描述
Digital Video Mixer

HSP48212 数据手册

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HSP48212  
Data Sheet  
May 1999  
File Number 3627.2  
Digital Video Mixer  
Features  
The Intersil HSP48212 is a 68 pin Digital Video Mixer IC  
intended for use in multimedia and medical imaging  
applications.  
• 12-Bit Pixel Data  
Two’s Complement or Unsigned Data  
• 12-Bit Mix Factor  
The HSP48212 allows the user to mix two video sources  
based on a programmable weighting factor. After weighting  
the input data signals, the Video Mixer simply adds the two  
weighted signals mathematically. This results in the mixed  
output, which is a weighted sum of the two sources.  
• 13-Bit Signed or Unsigned Three State Output  
• Overflow Detection and Output Saturation  
• Rounding to 8, 10, 12, or 13-Bits  
• Input and Output Pixel Data Synchronous to Clock  
The input and output interfaces are synchronous with respect  
to the input clock, simplifying the user interface requirements.  
• Programmable Pipeline Delay of up to 7 Clock Cycles for  
Control of Misaligned Input Data  
Input Data (DINA, DINB), Mix Factor (M) and control signals  
(RND, TCB) may be delayed relative to each other in order to  
compensate for any misalignment that may have occurred  
prior to entering the HSP48212. Each input’s delay may be  
independently programmed up to seven clock cycles.  
• TTL Compatible Inputs/Outputs  
• DC to 40MHz Clock Rate  
Applications  
The output data may be rounded to 8, 10, 12, or 13-bits. The  
enabling of data onto the output data bus is under the user’s  
control via an output enable signal (OE).  
• Video Summing (Frame Addition)  
• Video Mixing  
• Fade In/Out  
Ordering Information  
• Video Switching  
TEMP.  
o
• High Speed Multiplying  
PART NUMBER RANGE ( C)  
PACKAGE  
64 Ld MQFP  
68 Ld PLCC  
PKG. NO.  
Q64.14x14  
N68.95  
HSP48212VC-40  
HSP48212JC-40  
0 to 70  
0 to 70  
Block Diagram  
DELAY  
0-7  
TCB  
DELAY  
0-7  
DELAY  
0-7  
RND0-1  
DINB0-11  
2
12  
1-M  
SHIFT  
LEFT  
DELAY  
0-7  
M
DOUT0-12  
Σ
12  
12  
13  
DELAY  
0-7  
DINA0-11  
OE  
DOUT = 2 x [DINA x M + DINB x (1-M)]  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999  
1

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