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HSP45256GC-33 PDF预览

HSP45256GC-33

更新时间： 2024-01-04 17:02:53
品牌 Logo 应用领域
英特矽尔 - INTERSIL 外围集成电路时钟
页数 文件大小 规格书
23页 157K
描述
Binary Correlator

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中文翻译

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HSP45256GC-33 技术参数

生命周期：Contact Manufacturer零件包装代码：PGA
包装说明：,针数：85
Reach Compliance Code：unknownECCN代码：3A991.A.2
HTS代码：8542.39.00.01风险等级：5.65
Is Samacsys：N其他特性：ICC SPECIFIED @ 25.6MHZ
边界扫描：NO最大时钟频率：33 MHz
外部数据总线宽度：8JESD-30 代码：S-CPGA-P85
低功率模式：NO端子数量：85
最高工作温度：70 °C最低工作温度：
输出数据总线宽度：8封装主体材料：CERAMIC, METAL-SEALED COFIRED
封装形状：SQUARE封装形式：GRID ARRAY
认证状态：Not Qualified最大供电电压：5.25 V
最小供电电压：4.75 V标称供电电压：5 V
表面贴装：NO技术：CMOS
温度等级：COMMERCIAL端子形式：PIN/PEG
端子位置：PERPENDICULARuPs/uCs/外围集成电路类型：DSP PERIPHERAL, CORRELATOR
Base Number Matches：1

HSP45256GC-33 数据手册

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HSP45256  
Data Sheet  
May 1999  
File Number 2814.4  
Binary Correlator  
Features  
The Intersil HSP45256 is a high-speed, 256 tap binary  
correlator. It can be configured to perform one-dimensional  
or two-dimensional correlations of selectable data precision  
and length. Multiple HSP45256’s can be cascaded for  
increased correlation length. Unused taps can be masked  
out for reduced correlation length.  
• Reconfigurable 256 Stage Binary Correlator  
• 1-Bit Reference x 1, 2, 4, or 8-Bit Data  
• Separate Control and Reference Interfaces  
• 25.6, 33MHz Versions  
• Configurable for 1-D and 2-D Operation  
• Double Buffered Mask and Reference  
• Programmable Output Delay  
The correlation array consists of eight 32-tap stages. These  
may be cascaded internally to compare 1, 2, 4 or 8-bit input  
data with a 1-bit reference. Depending on the number of bits  
in the input data, the length of the correlation can be up to  
256, 128, 64, or 32 taps. The HSP45256 can also be  
configured as two separate correlators with window sizes  
from 4 by 32 to 1 by 128 each. The mask register can be  
used to prevent any subset of the 256 bits from contributing  
to the correlation score.  
• Cascadable  
• Standard Microprocessor Interface  
Applications  
• Radar/Sonar  
The output of the correlation array (correlation score) feeds  
the weight and sum logic, which gives added flexibility to the  
data format. In addition, an offset register is provided so that  
a preprogrammed value can be added to the correlation  
score. This result is then passed through a user  
programmable delay stage to the cascade summer. The  
delay stage simplifies the cascading of multiple correlators  
by compensating for the latency of previous correlators.  
• Spread Spectrum Communications  
• Pattern/Character Recognition  
- Error Correction Coding  
Ordering Information  
TEMP.  
o
PKG.  
NO.  
PART NUMBER RANGE ( C)  
PACKAGE  
84 Ld PLCC  
HSP45256JC-25  
HSP45256JC-33  
HSP45256GC-25  
HSP45256GC-33  
HSP45256JI-25  
HSP45256JI-33  
0 to 70  
0 to 70  
N84.1.15  
N84.1.15  
G85.A  
The Binary Correlator is configured by writing a set of control  
registers via a standard microprocessor interface. To simplify  
operation, both the control and reference registers are  
double buffered. This allows the user to load new mask and  
reference data while the current correlation is in progress.  
84 Ld PLCC  
85 Ld PGA  
85 Ld PGA  
84 Ld PLCC  
84 Ld PLCC  
0 to 70  
0 to 70  
G85.A  
-40 to 85  
-40 to 85  
N84.1.15  
N84.1.15  
Block Diagram  
DOUT  
DOUT0-7  
DIN0-7  
256 TAP  
CORRELATION  
ARRAY  
DREFOUT  
CSCORE  
AUXOUT0-8  
MUX  
DREF0-7  
WEIGHT  
AND SUM  
DCONT0-7  
A0-2  
CONTROL  
CASCADE  
SUMMER  
CASOUT0-12  
DELAY  
CASIN0-12  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999  
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