Datasheet > HSP45256

HSP45256

更新时间： 2024-02-09 02:23:44

品牌	Logo	应用领域
英特矽尔 - INTERSIL		/
页数	文件大小	规格书
23页	157K
描述
Binary Correlator

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数据手册

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HSP45256 数据手册

HSP45256

Data Sheet

May 1999

File Number 2814.4

Binary Correlator

Features

The Intersil HSP45256 is a high-speed, 256 tap binary

correlator. It can be conﬁgured to perform one-dimensional

or two-dimensional correlations of selectable data precision

and length. Multiple HSP45256’s can be cascaded for

increased correlation length. Unused taps can be masked

out for reduced correlation length.

• Reconﬁgurable 256 Stage Binary Correlator

• 1-Bit Reference x 1, 2, 4, or 8-Bit Data

• Separate Control and Reference Interfaces

• 25.6, 33MHz Versions

• Conﬁgurable for 1-D and 2-D Operation

• Double Buffered Mask and Reference

• Programmable Output Delay

The correlation array consists of eight 32-tap stages. These

may be cascaded internally to compare 1, 2, 4 or 8-bit input

data with a 1-bit reference. Depending on the number of bits

in the input data, the length of the correlation can be up to

256, 128, 64, or 32 taps. The HSP45256 can also be

conﬁgured as two separate correlators with window sizes

from 4 by 32 to 1 by 128 each. The mask register can be

used to prevent any subset of the 256 bits from contributing

to the correlation score.

• Cascadable

• Standard Microprocessor Interface

Applications

• Radar/Sonar

The output of the correlation array (correlation score) feeds

the weight and sum logic, which gives added ﬂexibility to the

data format. In addition, an offset register is provided so that

a preprogrammed value can be added to the correlation

score. This result is then passed through a user

programmable delay stage to the cascade summer. The

delay stage simpliﬁes the cascading of multiple correlators

by compensating for the latency of previous correlators.

• Spread Spectrum Communications

• Pattern/Character Recognition

- Error Correction Coding

Ordering Information

TEMP.

PKG.

NO.

PART NUMBER RANGE ( C)

PACKAGE

84 Ld PLCC

HSP45256JC-25

HSP45256JC-33

HSP45256GC-25

HSP45256GC-33

HSP45256JI-25

HSP45256JI-33

0 to 70

N84.1.15

G85.A

The Binary Correlator is conﬁgured by writing a set of control

registers via a standard microprocessor interface. To simplify

operation, both the control and reference registers are

double buffered. This allows the user to load new mask and

reference data while the current correlation is in progress.

84 Ld PLCC

85 Ld PGA

84 Ld PLCC

0 to 70

G85.A

-40 to 85

N84.1.15

Block Diagram

DOUT

DOUT0-7

DIN0-7

256 TAP

CORRELATION

ARRAY

DREFOUT

CSCORE

AUXOUT0-8

MUX

DREF0-7

WEIGHT

AND SUM

DCONT0-7

A0-2

CONTROL

CASCADE

SUMMER

CASOUT0-12

DELAY

CASIN0-12

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

12 3 4 5 6 7...23

中文翻译

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与HSP45256相关器件

型号	品牌	获取价格	描述	数据表
HSP45256/883	INTERSIL	获取价格	Binary Correlator
HSP45256883	INTERSIL	获取价格	Binary Correlator
HSP45256GC-25	INTERSIL	获取价格	Binary Correlator
HSP45256GC-25	RENESAS	获取价格	8-BIT, DSP-CORRELATOR, CPGA85, PGA-85
HSP45256GC-33	INTERSIL	获取价格	Binary Correlator
HSP45256GC-33	RENESAS	获取价格	8-BIT, DSP-CORRELATOR, CPGA85, PGA-85
HSP45256GM-20/883	INTERSIL	获取价格	Binary Correlator
HSP45256GM-25/883	INTERSIL	获取价格	Binary Correlator
HSP45256JC-25	INTERSIL	获取价格	Binary Correlator
HSP45256JC-33	INTERSIL	获取价格	Binary Correlator

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