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HSP45240GM-25/883 PDF预览

HSP45240GM-25/883

更新时间： 2024-02-19 15:00:15
品牌 Logo 应用领域
英特矽尔 - INTERSIL 外围集成电路双倍数据速率时钟
页数 文件大小 规格书
6页 145K
描述
Address Sequencer

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中文翻译

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HSP45240GM-25/883 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
包装说明：PGA, PGA68,11X11Reach Compliance Code：unknown
ECCN代码：3A001.A.2.CHTS代码：8542.39.00.01
风险等级：5.71其他特性：24 X 24 CROSSPOINT SWITCH; ICC SPECIFIED @ 33MHZ
边界扫描：NO最大时钟频率：25 MHz
外部数据总线宽度：7JESD-30 代码：S-CPGA-P68
JESD-609代码：e0低功率模式：NO
端子数量：68最高工作温度：125 °C
最低工作温度：-55 °C输出数据总线宽度：24
封装主体材料：CERAMIC, METAL-SEALED COFIRED封装代码：PGA
封装等效代码：PGA68,11X11封装形状：SQUARE
封装形式：GRID ARRAY电源：5 V
认证状态：Not Qualified筛选级别：38535Q/M;38534H;883B
子类别：Other Microprocessor ICs最大压摆率：99 mA
最大供电电压：5.5 V最小供电电压：4.5 V
标称供电电压：5 V表面贴装：NO
技术：CMOS温度等级：MILITARY
端子面层：Tin/Lead (Sn/Pb)端子形式：PIN/PEG
端子节距：2.54 mm端子位置：PERPENDICULAR
uPs/uCs/外围集成电路类型：DSP PERIPHERAL, ADDRESS SEQUENCERBase Number Matches：1

HSP45240GM-25/883 数据手册

 浏览型号HSP45240GM-25/883的Datasheet PDF文件第2页浏览型号HSP45240GM-25/883的Datasheet PDF文件第3页浏览型号HSP45240GM-25/883的Datasheet PDF文件第4页浏览型号HSP45240GM-25/883的Datasheet PDF文件第5页浏览型号HSP45240GM-25/883的Datasheet PDF文件第6页 
HSP45240/883  
Address Sequencer  
February 1998  
Features  
Description  
• This Circuit is Processed in Accordance to MIL-STD- The Intersil HSP45240/883 is a high speed Address  
883 and is Fully Conformant Under the Provisions of  
Paragraph 1.2.1.  
Sequencer which provides specialized addressing for func-  
tions like FFTs, 1-D and 2-D filtering, matrix operations, and  
image manipulation. The sequencer supports block oriented  
addressing of large data sets up to 24 bits at clock speeds  
up to 40MHz.  
• Block Oriented 24-Bit Sequencer  
• Configurable as Two Independent 12-Bit Sequencers  
• 24 x 24 Crosspoint Switch  
Specialized addressing requirements are met by using the  
onboard 24 x 24 crosspoint switch. This feature allows the  
mapping of the 24 address bits at the output of the address  
generator to the 24 address outputs of the chip. As a result,  
bit reverse addressing, such as that used in FFTs, is made  
possible.  
• Programmable Delay on 12 Outputs 9-  
• Multi-Chip Synchronization Signals  
• Standard µP Interface  
• 100pF Drive on Outputs  
A single chip solution to read/write addressing is also made  
possible by configuring the HSP45240 as two 12-bit  
sequencers. To compensate for system pipeline delay, a pro-  
grammable delay is provided on 12 of the address outputs.  
• DC to 40MHz Clock Rate  
Applications  
• 1-D, 2-D Filtering  
The HSP45240 is manufactured using an advanced CMOS  
process, and is a low power fully static design. The configu-  
ration of the device is controlled through a standard micro-  
processor interface and all inputs/outputs, with the exception  
of clock, are TTL compatible.  
• Pan/Zoom Addressing  
• FFT Processing  
• Matrix Math Operations  
Ordering Information  
TEMP.  
RANGE ( C)  
PKG.  
NO.  
o
PART NUMBER  
HSP45240GM-25/883  
HSP45240GM-33/883  
HSP45240GM-40/883  
PACKAGE  
-55 to 125 68 Ld PGA  
-55 to 125 68 Ld PGA  
-55 to 125 68 Ld PGA  
Block Diagram  
STARTOUT  
ADDVAL  
DONE  
BLOCKDONE  
12  
OUT12-23  
REG  
STARTIN  
24  
CROSS-POINT  
SWITCH  
START  
CIRCUITRY  
SEQUENCE  
GENERATOR  
OEH  
12  
DELAY  
1-8  
OUT0-11  
DLYBLK  
OEL  
BUSY  
PROCESSOR INTERFACE  
D0-6, CS, A0, WR  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
File Number 2816.3  
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999  
9-16  
123456

中文翻译

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