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HSP45240GC-33 PDF预览

HSP45240GC-33

更新时间： 2024-11-14 20:44:35
品牌 Logo 应用领域
瑞萨 - RENESAS 时钟双倍数据速率外围集成电路
页数 文件大小 规格书
13页 208K
描述
7-BIT, DSP-ADDRESS SEQUENCER, CPGA68, PGA-68

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HSP45240GC-33 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：PGA包装说明：PGA-68
针数：68Reach Compliance Code：not_compliant
ECCN代码：3A991.A.2HTS代码：8542.39.00.01
风险等级：5.71其他特性：24 X 24 CROSSPOINT SWITCH; ICC SPECIFIED AT 33MHZ
边界扫描：NO最大时钟频率：33 MHz
外部数据总线宽度：7JESD-30 代码：S-CPGA-P68
JESD-609代码：e0长度：29.465 mm
低功率模式：YES端子数量：68
最高工作温度：70 °C最低工作温度：
输出数据总线宽度：24封装主体材料：CERAMIC, METAL-SEALED COFIRED
封装代码：PGA封装等效代码：PGA68,11X11
封装形状：SQUARE封装形式：GRID ARRAY
峰值回流温度（摄氏度）：NOT SPECIFIED电源：5 V
认证状态：Not Qualified座面最大高度：5.2 mm
子类别：Other Microprocessor ICs最大供电电压：5.25 V
最小供电电压：4.75 V标称供电电压：5 V
表面贴装：NO技术：CMOS
温度等级：COMMERCIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：PIN/PEG端子节距：2.54 mm
端子位置：PERPENDICULAR处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：29.465 mmuPs/uCs/外围集成电路类型：DSP PERIPHERAL, ADDRESS SEQUENCER
Base Number Matches：1

HSP45240GC-33 数据手册

 浏览型号HSP45240GC-33的Datasheet PDF文件第2页浏览型号HSP45240GC-33的Datasheet PDF文件第3页浏览型号HSP45240GC-33的Datasheet PDF文件第4页浏览型号HSP45240GC-33的Datasheet PDF文件第5页浏览型号HSP45240GC-33的Datasheet PDF文件第6页浏览型号HSP45240GC-33的Datasheet PDF文件第7页 
TM  
HSP45240  
September 1997  
Address Sequencer  
Features  
Description  
• Block Oriented 24-Bit Sequencer  
• Configurable as Two Independent 12-Bit Sequencers  
• 24 x 24 Crosspoint Switch  
The Intersil HSP45240 is a high speed Address Sequencer  
which provides specialized addressing for functions like  
FFTs, 1-D and 2-D filtering, matrix operations, and image  
manipulation. The sequencer supports block oriented  
addressing of large data sets up to 24-bits at clock speeds  
up to 50MHz.  
• Programmable Delay on 12 Outputs  
• Multi-Chip Synchronization Signals  
• Standard µP Interface  
Specialized addressing requirements are met by using the  
onboard 24 x 24 crosspoint switch. This feature allows the map-  
ping of the 24 address bits at the output of the address genera-  
tor to the 24 address outputs of the chip. As a result, bit reverse  
addressing, such as that used in FFTs, is made possible.  
• 100pF Drive on Outputs  
• DC to 50MHz Clock Rate  
A single chip solution to read/write addressing is also made  
possible by configuring the HSP45240 as two 12-bit  
sequencers. To compensate for system pipeline delay, a pro-  
grammable delay is provided on 12 of the address outputs.  
Applications  
• 1-D, 2-D Filtering  
• Pan/Zoom Addressing  
• FFT Processing  
The HSP45240 is manufactured using an advanced CMOS  
process, and is a low power fully static design. The configu-  
ration of the device is controlled through a standard micro-  
processor interface and all inputs/outputs, with the exception  
of clock, are TTL compatible.  
• Matrix Math Operations  
Ordering Information  
TEMP.  
PKG.  
NO.  
o
PART NUMBER RANGE ( C)  
PACKAGE  
68 Ld PLCC  
68 Ld PLCC  
68 Ld PLCC  
68 Ld PGA  
HSP45240JC-33  
HSP45240JC-40  
HSP45240JC-50  
HSP45240GC-33  
HSP45240GC-40  
HSP45240GC-50  
0 to 70  
0 to 70  
0 to 70  
0 to 70  
0 to 70  
0 to 70  
N68.95  
N68.95  
N68.95  
G68.A  
G68.A  
G68.A  
68 Ld PGA  
68 Ld PGA  
Block Diagram  
STARTOUT  
ADDVAL  
DONE  
BLOCKDONE  
12  
OUT12-23  
REG  
STARTIN  
24  
START  
CIRCUITRY  
SEQUENCE  
GENERATOR  
CROSSPOINT  
SWITCH  
OEH  
12  
DELAY  
1-8  
OUT0-11  
DLYBLK  
OEL  
BUSY  
PROCESSOR INTERFACE  
D0-6, CS, A0, WR  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc.  
File Number 2489.3  
Copyright © Intersil Americas Inc. 2002. All Rights Reserved  
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